xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_rt_defs.h (revision 14b24e2b79293068c8e016a69ef1d872fb5e2fd5)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #ifndef __RT_DEFS_H__
37 #define __RT_DEFS_H__
38 
39 /* Runtime array offsets */
40 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                            	0
41 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                            	1
42 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                            	2
43 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                            	3
44 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                            	4
45 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                            	5
46 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                            	6
47 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                            	7
48 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                            	8
49 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                            	9
50 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                            	10
51 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                            	11
52 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                            	12
53 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                            	13
54 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                            	14
55 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                            	15
56 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                              	16
57 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET                           	17
58 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET                          	18
59 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET                          	19
60 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                           	20
61 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                           	21
62 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                        	22
63 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                       	23
64 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                         	24
65 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                             	761
66 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                               	736
67 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                             	761
68 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                               	736
69 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                            	1497
70 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                              	736
71 #define CAU_REG_PI_MEMORY_RT_OFFSET                                 	2233
72 #define CAU_REG_PI_MEMORY_RT_SIZE                                   	4416
73 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET                	6649
74 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET                  	6650
75 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET                  	6651
76 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                     	6652
77 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                     	6653
78 #define PRS_REG_SEARCH_TCP_RT_OFFSET                                	6654
79 #define PRS_REG_SEARCH_FCOE_RT_OFFSET                               	6655
80 #define PRS_REG_SEARCH_ROCE_RT_OFFSET                               	6656
81 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET                       	6657
82 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET                       	6658
83 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                           	6659
84 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET                 	6660
85 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET       	6661
86 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET                  	6662
87 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET                           	6663
88 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                     	6664
89 #define SRC_REG_FIRSTFREE_RT_OFFSET                                 	6665
90 #define SRC_REG_FIRSTFREE_RT_SIZE                                   	2
91 #define SRC_REG_LASTFREE_RT_OFFSET                                  	6667
92 #define SRC_REG_LASTFREE_RT_SIZE                                    	2
93 #define SRC_REG_COUNTFREE_RT_OFFSET                                 	6669
94 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                          	6670
95 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                            	6671
96 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                            	6672
97 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                              	6673
98 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                              	6674
99 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                             	6675
100 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET                            	6676
101 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                           	6677
102 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                            	6678
103 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                           	6679
104 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                            	6680
105 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                          	6681
106 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                           	6682
107 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                         	6683
108 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                          	6684
109 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                         	6685
110 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                          	6686
111 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                         	6687
112 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                          	6688
113 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET                 	6689
114 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET               	6690
115 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET               	6691
116 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                           	6692
117 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                         	6693
118 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                         	6694
119 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                       	6695
120 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                     	6696
121 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                     	6697
122 #define PSWRQ2_REG_VF_BASE_RT_OFFSET                                	6698
123 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                            	6699
124 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                          	6700
125 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                          	6701
126 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                             	6702
127 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                               	22000
128 #define PGLUE_REG_B_VF_BASE_RT_OFFSET                               	28702
129 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET                    	28703
130 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET                       	28704
131 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET                       	28705
132 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET                          	28706
133 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET                          	28707
134 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET                          	28708
135 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET                             	28709
136 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET                             	28710
137 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET                             	28711
138 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET                 	28712
139 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET                 	28713
140 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET                            	28714
141 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE                              	416
142 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET                            	29130
143 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE                              	608
144 #define QM_REG_MAXPQSIZE_0_RT_OFFSET                                	29738
145 #define QM_REG_MAXPQSIZE_1_RT_OFFSET                                	29739
146 #define QM_REG_MAXPQSIZE_2_RT_OFFSET                                	29740
147 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET                           	29741
148 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET                           	29742
149 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET                           	29743
150 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET                           	29744
151 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET                           	29745
152 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET                           	29746
153 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET                           	29747
154 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET                           	29748
155 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET                           	29749
156 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET                           	29750
157 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET                          	29751
158 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET                          	29752
159 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET                          	29753
160 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET                          	29754
161 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET                          	29755
162 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET                          	29756
163 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET                          	29757
164 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET                          	29758
165 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET                          	29759
166 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET                          	29760
167 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET                          	29761
168 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET                          	29762
169 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET                          	29763
170 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET                          	29764
171 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET                          	29765
172 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET                          	29766
173 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET                          	29767
174 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET                          	29768
175 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET                          	29769
176 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET                          	29770
177 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET                          	29771
178 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET                          	29772
179 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET                          	29773
180 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET                          	29774
181 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET                          	29775
182 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET                          	29776
183 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET                          	29777
184 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET                          	29778
185 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET                          	29779
186 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET                          	29780
187 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET                          	29781
188 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET                          	29782
189 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET                          	29783
190 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET                          	29784
191 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET                          	29785
192 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET                          	29786
193 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET                          	29787
194 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET                          	29788
195 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET                          	29789
196 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET                          	29790
197 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET                          	29791
198 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET                          	29792
199 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET                          	29793
200 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET                          	29794
201 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET                          	29795
202 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET                          	29796
203 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET                          	29797
204 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET                          	29798
205 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET                          	29799
206 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET                          	29800
207 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET                          	29801
208 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET                          	29802
209 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET                          	29803
210 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET                          	29804
211 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET                            	29805
212 #define QM_REG_BASEADDROTHERPQ_RT_SIZE                              	128
213 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET                         	29933
214 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET                         	29934
215 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET                          	29935
216 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET                        	29936
217 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET                       	29937
218 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET                            	29938
219 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET                            	29939
220 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET                            	29940
221 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET                            	29941
222 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET                            	29942
223 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET                            	29943
224 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET                            	29944
225 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET                            	29945
226 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET                            	29946
227 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET                            	29947
228 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET                           	29948
229 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET                           	29949
230 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET                           	29950
231 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET                           	29951
232 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET                           	29952
233 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET                           	29953
234 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET                        	29954
235 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET                        	29955
236 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET                        	29956
237 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET                        	29957
238 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET                           	29958
239 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET                           	29959
240 #define QM_REG_PQTX2PF_0_RT_OFFSET                                  	29960
241 #define QM_REG_PQTX2PF_1_RT_OFFSET                                  	29961
242 #define QM_REG_PQTX2PF_2_RT_OFFSET                                  	29962
243 #define QM_REG_PQTX2PF_3_RT_OFFSET                                  	29963
244 #define QM_REG_PQTX2PF_4_RT_OFFSET                                  	29964
245 #define QM_REG_PQTX2PF_5_RT_OFFSET                                  	29965
246 #define QM_REG_PQTX2PF_6_RT_OFFSET                                  	29966
247 #define QM_REG_PQTX2PF_7_RT_OFFSET                                  	29967
248 #define QM_REG_PQTX2PF_8_RT_OFFSET                                  	29968
249 #define QM_REG_PQTX2PF_9_RT_OFFSET                                  	29969
250 #define QM_REG_PQTX2PF_10_RT_OFFSET                                 	29970
251 #define QM_REG_PQTX2PF_11_RT_OFFSET                                 	29971
252 #define QM_REG_PQTX2PF_12_RT_OFFSET                                 	29972
253 #define QM_REG_PQTX2PF_13_RT_OFFSET                                 	29973
254 #define QM_REG_PQTX2PF_14_RT_OFFSET                                 	29974
255 #define QM_REG_PQTX2PF_15_RT_OFFSET                                 	29975
256 #define QM_REG_PQTX2PF_16_RT_OFFSET                                 	29976
257 #define QM_REG_PQTX2PF_17_RT_OFFSET                                 	29977
258 #define QM_REG_PQTX2PF_18_RT_OFFSET                                 	29978
259 #define QM_REG_PQTX2PF_19_RT_OFFSET                                 	29979
260 #define QM_REG_PQTX2PF_20_RT_OFFSET                                 	29980
261 #define QM_REG_PQTX2PF_21_RT_OFFSET                                 	29981
262 #define QM_REG_PQTX2PF_22_RT_OFFSET                                 	29982
263 #define QM_REG_PQTX2PF_23_RT_OFFSET                                 	29983
264 #define QM_REG_PQTX2PF_24_RT_OFFSET                                 	29984
265 #define QM_REG_PQTX2PF_25_RT_OFFSET                                 	29985
266 #define QM_REG_PQTX2PF_26_RT_OFFSET                                 	29986
267 #define QM_REG_PQTX2PF_27_RT_OFFSET                                 	29987
268 #define QM_REG_PQTX2PF_28_RT_OFFSET                                 	29988
269 #define QM_REG_PQTX2PF_29_RT_OFFSET                                 	29989
270 #define QM_REG_PQTX2PF_30_RT_OFFSET                                 	29990
271 #define QM_REG_PQTX2PF_31_RT_OFFSET                                 	29991
272 #define QM_REG_PQTX2PF_32_RT_OFFSET                                 	29992
273 #define QM_REG_PQTX2PF_33_RT_OFFSET                                 	29993
274 #define QM_REG_PQTX2PF_34_RT_OFFSET                                 	29994
275 #define QM_REG_PQTX2PF_35_RT_OFFSET                                 	29995
276 #define QM_REG_PQTX2PF_36_RT_OFFSET                                 	29996
277 #define QM_REG_PQTX2PF_37_RT_OFFSET                                 	29997
278 #define QM_REG_PQTX2PF_38_RT_OFFSET                                 	29998
279 #define QM_REG_PQTX2PF_39_RT_OFFSET                                 	29999
280 #define QM_REG_PQTX2PF_40_RT_OFFSET                                 	30000
281 #define QM_REG_PQTX2PF_41_RT_OFFSET                                 	30001
282 #define QM_REG_PQTX2PF_42_RT_OFFSET                                 	30002
283 #define QM_REG_PQTX2PF_43_RT_OFFSET                                 	30003
284 #define QM_REG_PQTX2PF_44_RT_OFFSET                                 	30004
285 #define QM_REG_PQTX2PF_45_RT_OFFSET                                 	30005
286 #define QM_REG_PQTX2PF_46_RT_OFFSET                                 	30006
287 #define QM_REG_PQTX2PF_47_RT_OFFSET                                 	30007
288 #define QM_REG_PQTX2PF_48_RT_OFFSET                                 	30008
289 #define QM_REG_PQTX2PF_49_RT_OFFSET                                 	30009
290 #define QM_REG_PQTX2PF_50_RT_OFFSET                                 	30010
291 #define QM_REG_PQTX2PF_51_RT_OFFSET                                 	30011
292 #define QM_REG_PQTX2PF_52_RT_OFFSET                                 	30012
293 #define QM_REG_PQTX2PF_53_RT_OFFSET                                 	30013
294 #define QM_REG_PQTX2PF_54_RT_OFFSET                                 	30014
295 #define QM_REG_PQTX2PF_55_RT_OFFSET                                 	30015
296 #define QM_REG_PQTX2PF_56_RT_OFFSET                                 	30016
297 #define QM_REG_PQTX2PF_57_RT_OFFSET                                 	30017
298 #define QM_REG_PQTX2PF_58_RT_OFFSET                                 	30018
299 #define QM_REG_PQTX2PF_59_RT_OFFSET                                 	30019
300 #define QM_REG_PQTX2PF_60_RT_OFFSET                                 	30020
301 #define QM_REG_PQTX2PF_61_RT_OFFSET                                 	30021
302 #define QM_REG_PQTX2PF_62_RT_OFFSET                                 	30022
303 #define QM_REG_PQTX2PF_63_RT_OFFSET                                 	30023
304 #define QM_REG_PQOTHER2PF_0_RT_OFFSET                               	30024
305 #define QM_REG_PQOTHER2PF_1_RT_OFFSET                               	30025
306 #define QM_REG_PQOTHER2PF_2_RT_OFFSET                               	30026
307 #define QM_REG_PQOTHER2PF_3_RT_OFFSET                               	30027
308 #define QM_REG_PQOTHER2PF_4_RT_OFFSET                               	30028
309 #define QM_REG_PQOTHER2PF_5_RT_OFFSET                               	30029
310 #define QM_REG_PQOTHER2PF_6_RT_OFFSET                               	30030
311 #define QM_REG_PQOTHER2PF_7_RT_OFFSET                               	30031
312 #define QM_REG_PQOTHER2PF_8_RT_OFFSET                               	30032
313 #define QM_REG_PQOTHER2PF_9_RT_OFFSET                               	30033
314 #define QM_REG_PQOTHER2PF_10_RT_OFFSET                              	30034
315 #define QM_REG_PQOTHER2PF_11_RT_OFFSET                              	30035
316 #define QM_REG_PQOTHER2PF_12_RT_OFFSET                              	30036
317 #define QM_REG_PQOTHER2PF_13_RT_OFFSET                              	30037
318 #define QM_REG_PQOTHER2PF_14_RT_OFFSET                              	30038
319 #define QM_REG_PQOTHER2PF_15_RT_OFFSET                              	30039
320 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET                             	30040
321 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET                             	30041
322 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET                        	30042
323 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET                        	30043
324 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET                          	30044
325 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET                          	30045
326 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET                          	30046
327 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET                          	30047
328 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET                          	30048
329 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET                          	30049
330 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET                          	30050
331 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET                          	30051
332 #define QM_REG_RLGLBLINCVAL_RT_OFFSET                               	30052
333 #define QM_REG_RLGLBLINCVAL_RT_SIZE                                 	256
334 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET                           	30308
335 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                             	256
336 #define QM_REG_RLGLBLCRD_RT_OFFSET                                  	30564
337 #define QM_REG_RLGLBLCRD_RT_SIZE                                    	256
338 #define QM_REG_RLGLBLENABLE_RT_OFFSET                               	30820
339 #define QM_REG_RLPFPERIOD_RT_OFFSET                                 	30821
340 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET                            	30822
341 #define QM_REG_RLPFINCVAL_RT_OFFSET                                 	30823
342 #define QM_REG_RLPFINCVAL_RT_SIZE                                   	16
343 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET                             	30839
344 #define QM_REG_RLPFUPPERBOUND_RT_SIZE                               	16
345 #define QM_REG_RLPFCRD_RT_OFFSET                                    	30855
346 #define QM_REG_RLPFCRD_RT_SIZE                                      	16
347 #define QM_REG_RLPFENABLE_RT_OFFSET                                 	30871
348 #define QM_REG_RLPFVOQENABLE_RT_OFFSET                              	30872
349 #define QM_REG_WFQPFWEIGHT_RT_OFFSET                                	30873
350 #define QM_REG_WFQPFWEIGHT_RT_SIZE                                  	16
351 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET                            	30889
352 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE                              	16
353 #define QM_REG_WFQPFCRD_RT_OFFSET                                   	30905
354 #define QM_REG_WFQPFCRD_RT_SIZE                                     	256
355 #define QM_REG_WFQPFENABLE_RT_OFFSET                                	31161
356 #define QM_REG_WFQVPENABLE_RT_OFFSET                                	31162
357 #define QM_REG_BASEADDRTXPQ_RT_OFFSET                               	31163
358 #define QM_REG_BASEADDRTXPQ_RT_SIZE                                 	512
359 #define QM_REG_TXPQMAP_RT_OFFSET                                    	31675
360 #define QM_REG_TXPQMAP_RT_SIZE                                      	512
361 #define QM_REG_WFQVPWEIGHT_RT_OFFSET                                	32187
362 #define QM_REG_WFQVPWEIGHT_RT_SIZE                                  	512
363 #define QM_REG_WFQVPCRD_RT_OFFSET                                   	32699
364 #define QM_REG_WFQVPCRD_RT_SIZE                                     	512
365 #define QM_REG_WFQVPMAP_RT_OFFSET                                   	33211
366 #define QM_REG_WFQVPMAP_RT_SIZE                                     	512
367 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET                               	33723
368 #define QM_REG_WFQPFCRD_MSB_RT_SIZE                                 	320
369 #define QM_REG_VOQCRDLINE_RT_OFFSET                                 	34043
370 #define QM_REG_VOQCRDLINE_RT_SIZE                                   	36
371 #define QM_REG_VOQINITCRDLINE_RT_OFFSET                             	34079
372 #define QM_REG_VOQINITCRDLINE_RT_SIZE                               	36
373 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET                           	34115
374 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET                     	34116
375 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET                     	34117
376 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET                     	34118
377 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET                     	34119
378 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET                      	34120
379 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET                  	34121
380 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET                           	34122
381 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                             	4
382 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET                      	34126
383 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE                        	4
384 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET                        	34130
385 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                          	4
386 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET                           	34134
387 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET                     	34135
388 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                       	32
389 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET                        	34167
390 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                          	16
391 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET                      	34183
392 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                        	16
393 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET             	34199
394 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE               	16
395 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET                   	34215
396 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                     	16
397 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET                              	34231
398 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET                    	34232
399 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                           	34233
400 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                           	34234
401 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                           	34235
402 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                       	34236
403 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                       	34237
404 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                       	34238
405 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                       	34239
406 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                    	34240
407 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                    	34241
408 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                    	34242
409 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                    	34243
410 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                        	34244
411 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                     	34245
412 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET                           	34246
413 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                      	34247
414 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                    	34248
415 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                       	34249
416 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET                	34250
417 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                    	34251
418 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                       	34252
419 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET                	34253
420 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                    	34254
421 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                       	34255
422 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET                	34256
423 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                    	34257
424 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                       	34258
425 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET                	34259
426 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                    	34260
427 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                       	34261
428 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET                	34262
429 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                    	34263
430 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                       	34264
431 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET                	34265
432 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                    	34266
433 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                       	34267
434 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET                	34268
435 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                    	34269
436 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                       	34270
437 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET                	34271
438 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                    	34272
439 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                       	34273
440 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET                	34274
441 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                    	34275
442 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                       	34276
443 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET                	34277
444 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET                   	34278
445 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                      	34279
446 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET               	34280
447 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET                   	34281
448 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                      	34282
449 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET               	34283
450 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET                   	34284
451 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                      	34285
452 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET               	34286
453 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET                   	34287
454 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                      	34288
455 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET               	34289
456 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET                   	34290
457 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                      	34291
458 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET               	34292
459 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET                   	34293
460 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                      	34294
461 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET               	34295
462 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET                   	34296
463 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                      	34297
464 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET               	34298
465 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET                   	34299
466 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                      	34300
467 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET               	34301
468 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET                   	34302
469 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                      	34303
470 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET               	34304
471 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET                   	34305
472 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                      	34306
473 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET               	34307
474 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                                	34308
475 
476 #define RUNTIME_ARRAY_SIZE 34309
477 
478 #endif /* __RT_DEFS_H__ */
479