1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __COMMON_HSI__ 37 #define __COMMON_HSI__ 38 /********************************/ 39 /* PROTOCOL COMMON FW CONSTANTS */ 40 /********************************/ 41 42 /* Temporarily here should be added to HSI automatically by resource allocation tool.*/ 43 #define T_TEST_AGG_INT_TEMP 6 44 #define M_TEST_AGG_INT_TEMP 8 45 #define U_TEST_AGG_INT_TEMP 6 46 #define X_TEST_AGG_INT_TEMP 14 47 #define Y_TEST_AGG_INT_TEMP 4 48 #define P_TEST_AGG_INT_TEMP 4 49 50 #define X_FINAL_CLEANUP_AGG_INT 1 51 52 #define EVENT_RING_PAGE_SIZE_BYTES 4096 53 54 #define NUM_OF_GLOBAL_QUEUES 128 55 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 56 57 #define ISCSI_CDU_TASK_SEG_TYPE 0 58 #define FCOE_CDU_TASK_SEG_TYPE 0 59 #define RDMA_CDU_TASK_SEG_TYPE 1 60 61 #define FW_ASSERT_GENERAL_ATTN_IDX 32 62 63 #define MAX_PINNED_CCFC 32 64 65 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 66 67 /* Queue Zone sizes in bytes */ 68 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 69 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ 70 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 71 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 72 #define YSTORM_QZONE_SIZE 0 73 #define PSTORM_QZONE_SIZE 0 74 75 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ 76 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ 77 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ 78 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ 79 80 81 /********************************/ 82 /* CORE (LIGHT L2) FW CONSTANTS */ 83 /********************************/ 84 85 #define CORE_LL2_MAX_RAMROD_PER_CON 8 86 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 87 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 88 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 89 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 90 91 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 92 93 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 94 95 /* 96 * Usually LL2 queues are opened in pairs � TX-RX. 97 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). 98 * Number of TX queues is almost unlimited. 99 * The constants are different so as to allow asymmetric LL2 connections 100 */ 101 102 #define MAX_NUM_LL2_RX_QUEUES 48 103 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 104 105 106 /////////////////////////////////////////////////////////////////////////////////////////////////// 107 // Include firmware verison number only- do not add constants here to avoid redundunt compilations 108 /////////////////////////////////////////////////////////////////////////////////////////////////// 109 110 111 #define FW_MAJOR_VERSION 8 112 #define FW_MINOR_VERSION 18 113 #define FW_REVISION_VERSION 19 114 #define FW_ENGINEERING_VERSION 0 115 116 /***********************/ 117 /* COMMON HW CONSTANTS */ 118 /***********************/ 119 120 /* PCI functions */ 121 #define MAX_NUM_PORTS_K2 (4) 122 #define MAX_NUM_PORTS_BB (2) 123 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 124 125 #define MAX_NUM_PFS_K2 (16) 126 #define MAX_NUM_PFS_BB (8) 127 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 128 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 129 130 #define MAX_NUM_VFS_BB (120) 131 #define MAX_NUM_VFS_K2 (192) 132 #define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2) 133 #define E5_MAX_NUM_VFS (240) 134 #define COMMON_MAX_NUM_VFS (E5_MAX_NUM_VFS) 135 136 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 137 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 138 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS) 139 140 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ 141 /* possible PFs and VFs - we need a constant for this size */ 142 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 143 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 144 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS) 145 146 #define MAX_NUM_VPORTS_K2 (208) 147 #define MAX_NUM_VPORTS_BB (160) 148 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 149 150 #define MAX_NUM_L2_QUEUES_K2 (320) 151 #define MAX_NUM_L2_QUEUES_BB (256) 152 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 153 154 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 155 // 4-Port K2. 156 #define NUM_PHYS_TCS_4PORT_K2 (4) 157 #define NUM_OF_PHYS_TCS (8) 158 159 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 160 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 161 162 #define LB_TC (NUM_OF_PHYS_TCS) 163 164 /* Num of possible traffic priority values */ 165 #define NUM_OF_PRIO (8) 166 167 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 168 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 169 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 170 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) 171 172 /* CIDs */ 173 #define E4_NUM_OF_CONNECTION_TYPES (8) 174 #define E5_NUM_OF_CONNECTION_TYPES (16) 175 #define NUM_OF_TASK_TYPES (8) 176 #define NUM_OF_LCIDS (320) 177 #define NUM_OF_LTIDS (320) 178 179 /* Clock values */ 180 #define MASTER_CLK_FREQ_E4 (375e6) 181 #define STORM_CLK_FREQ_E4 (1000e6) 182 #define CLK25M_CLK_FREQ_E4 (25e6) 183 184 #define STORM_CLK_DUAL_CORE_FREQ_E5 (3000e6) 185 186 /* Global PXP windows (GTT) */ 187 #define NUM_OF_GTT 19 188 #define GTT_DWORD_SIZE_BITS 10 189 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 190 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 191 192 /* Tools Version */ 193 #define TOOLS_VERSION 10 194 /*****************/ 195 /* CDU CONSTANTS */ 196 /*****************/ 197 198 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 199 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 200 201 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 202 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 203 204 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 205 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 206 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 207 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 208 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 209 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 210 211 212 /*****************/ 213 /* DQ CONSTANTS */ 214 /*****************/ 215 216 /* DEMS */ 217 #define DQ_DEMS_LEGACY 0 218 #define DQ_DEMS_TOE_MORE_TO_SEND 3 219 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 220 #define DQ_DEMS_ROCE_CQ_CONS 7 221 222 /* XCM agg val selection (HW) */ 223 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 224 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 225 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 226 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 227 #define DQ_XCM_AGG_VAL_SEL_REG3 4 228 #define DQ_XCM_AGG_VAL_SEL_REG4 5 229 #define DQ_XCM_AGG_VAL_SEL_REG5 6 230 #define DQ_XCM_AGG_VAL_SEL_REG6 7 231 232 /* XCM agg val selection (FW) */ 233 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 234 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 235 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 236 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 237 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 238 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 239 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 240 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 241 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 242 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 243 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 244 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 245 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 246 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 247 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 248 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 249 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 250 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 251 252 /* UCM agg val selection (HW) */ 253 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 254 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 255 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 256 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 257 #define DQ_UCM_AGG_VAL_SEL_REG0 4 258 #define DQ_UCM_AGG_VAL_SEL_REG1 5 259 #define DQ_UCM_AGG_VAL_SEL_REG2 6 260 #define DQ_UCM_AGG_VAL_SEL_REG3 7 261 262 /* UCM agg val selection (FW) */ 263 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 264 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 265 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 266 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 267 268 /* TCM agg val selection (HW) */ 269 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 270 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 271 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 272 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 273 #define DQ_TCM_AGG_VAL_SEL_REG1 4 274 #define DQ_TCM_AGG_VAL_SEL_REG2 5 275 #define DQ_TCM_AGG_VAL_SEL_REG6 6 276 #define DQ_TCM_AGG_VAL_SEL_REG9 7 277 278 /* TCM agg val selection (FW) */ 279 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 280 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 281 282 /* XCM agg counter flag selection (HW) */ 283 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 284 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 285 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 286 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 287 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 288 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 289 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 290 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 291 292 /* XCM agg counter flag selection (FW) */ 293 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 294 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 295 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 296 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 297 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 298 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 299 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 300 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 301 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 302 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 303 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 304 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 305 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 306 307 /* UCM agg counter flag selection (HW) */ 308 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 309 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 310 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 311 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 312 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 313 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 314 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 315 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 316 317 /* UCM agg counter flag selection (FW) */ 318 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 319 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 320 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 321 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 322 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 323 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 324 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 325 326 /* TCM agg counter flag selection (HW) */ 327 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 328 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 329 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 330 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 331 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 332 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 333 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 334 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 335 336 /* TCM agg counter flag selection (FW) */ 337 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 338 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 339 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 340 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 341 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 342 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 343 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 344 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 345 346 /* PWM address mapping */ 347 #define DQ_PWM_OFFSET_DPM_BASE 0x0 348 #define DQ_PWM_OFFSET_DPM_END 0x27 349 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 350 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 351 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 352 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 353 #define DQ_PWM_OFFSET_UCM16_4 0x50 354 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 355 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 356 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 357 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 358 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 359 360 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 361 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 362 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 363 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 364 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 365 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 366 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 367 368 #define DQ_REGION_SHIFT (12) 369 370 /* DPM */ 371 #define DQ_DPM_WQE_BUFF_SIZE (320) 372 373 // Conn type ranges 374 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 375 376 /*****************/ 377 /* QM CONSTANTS */ 378 /*****************/ 379 380 /* number of TX queues in the QM */ 381 #define MAX_QM_TX_QUEUES_K2 512 382 #define MAX_QM_TX_QUEUES_BB 448 383 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 384 385 /* number of Other queues in the QM */ 386 #define MAX_QM_OTHER_QUEUES_BB 64 387 #define MAX_QM_OTHER_QUEUES_K2 128 388 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 389 390 /* number of queues in a PF queue group */ 391 #define QM_PF_QUEUE_GROUP_SIZE 8 392 393 /* the size of a single queue element in bytes */ 394 #define QM_PQ_ELEMENT_SIZE 4 395 396 /* base number of Tx PQs in the CM PQ representation. 397 should be used when storing PQ IDs in CM PQ registers and context */ 398 #define CM_TX_PQ_BASE 0x200 399 400 /* number of global Vport/QCN rate limiters */ 401 #define MAX_QM_GLOBAL_RLS 256 402 403 /* QM registers data */ 404 #define QM_LINE_CRD_REG_WIDTH 16 405 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 406 #define QM_BYTE_CRD_REG_WIDTH 24 407 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 408 #define QM_WFQ_CRD_REG_WIDTH 32 409 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 410 #define QM_RL_CRD_REG_WIDTH 32 411 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 412 413 /*****************/ 414 /* CAU CONSTANTS */ 415 /*****************/ 416 417 #define CAU_FSM_ETH_RX 0 418 #define CAU_FSM_ETH_TX 1 419 420 /* Number of Protocol Indices per Status Block */ 421 #define PIS_PER_SB 12 422 423 424 #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ 425 #define CAU_HC_DISABLE_STATE 4 /* fsm is working without interrupt coalescing for this sb*/ 426 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/ 427 428 429 /*****************/ 430 /* IGU CONSTANTS */ 431 /*****************/ 432 433 #define MAX_SB_PER_PATH_K2 (368) 434 #define MAX_SB_PER_PATH_BB (288) 435 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_K2 436 437 #define MAX_SB_PER_PF_MIMD 129 438 #define MAX_SB_PER_PF_SIMD 64 439 #define MAX_SB_PER_VF 64 440 441 /* Memory addresses on the BAR for the IGU Sub Block */ 442 #define IGU_MEM_BASE 0x0000 443 444 #define IGU_MEM_MSIX_BASE 0x0000 445 #define IGU_MEM_MSIX_UPPER 0x0101 446 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 447 448 #define IGU_MEM_PBA_MSIX_BASE 0x0200 449 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 450 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 451 452 #define IGU_CMD_INT_ACK_BASE 0x0400 453 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_TOT_SB_PER_PATH - 1) 454 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 455 456 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 457 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 458 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 459 460 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 461 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 462 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 463 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 464 465 #define IGU_CMD_PROD_UPD_BASE 0x0600 466 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + MAX_TOT_SB_PER_PATH - 1) 467 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 468 469 /*****************/ 470 /* PXP CONSTANTS */ 471 /*****************/ 472 473 /* Bars for Blocks */ 474 #define PXP_BAR_GRC 0 475 #define PXP_BAR_TSDM 0 476 #define PXP_BAR_USDM 0 477 #define PXP_BAR_XSDM 0 478 #define PXP_BAR_MSDM 0 479 #define PXP_BAR_YSDM 0 480 #define PXP_BAR_PSDM 0 481 #define PXP_BAR_IGU 0 482 #define PXP_BAR_DQ 1 483 484 /* PTT and GTT */ 485 #define PXP_PER_PF_ENTRY_SIZE 8 486 #define PXP_NUM_GLOBAL_WINDOWS 243 487 #define PXP_GLOBAL_ENTRY_SIZE 4 488 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 489 #define PXP_PF_WINDOW_ADMIN_START 0 490 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 491 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_LENGTH - 1) 492 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 493 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * PXP_PER_PF_ENTRY_SIZE) 494 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 495 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 496 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * PXP_GLOBAL_ENTRY_SIZE) 497 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END (PXP_PF_WINDOW_ADMIN_GLOBAL_START + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 498 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 499 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 500 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 501 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 502 503 #define PXP_NUM_PF_WINDOWS 12 504 505 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 506 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 507 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 508 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 509 #define PXP_EXTERNAL_BAR_PF_WINDOW_END (PXP_EXTERNAL_BAR_PF_WINDOW_START + PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 510 511 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 512 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 513 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 514 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 515 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 516 517 /* PF BAR */ 518 #define PXP_BAR0_START_GRC 0x0000 519 #define PXP_BAR0_GRC_LENGTH 0x1C00000 520 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 521 522 #define PXP_BAR0_START_IGU 0x1C00000 523 #define PXP_BAR0_IGU_LENGTH 0x10000 524 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 525 526 #define PXP_BAR0_START_TSDM 0x1C80000 527 #define PXP_BAR0_SDM_LENGTH 0x40000 528 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 529 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 530 531 #define PXP_BAR0_START_MSDM 0x1D00000 532 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 533 534 #define PXP_BAR0_START_USDM 0x1D80000 535 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 536 537 #define PXP_BAR0_START_XSDM 0x1E00000 538 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 539 540 #define PXP_BAR0_START_YSDM 0x1E80000 541 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 542 543 #define PXP_BAR0_START_PSDM 0x1F00000 544 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 545 546 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 547 548 /* VF BAR */ 549 #define PXP_VF_BAR0 0 550 551 #define PXP_VF_BAR0_START_GRC 0x3E00 552 #define PXP_VF_BAR0_GRC_LENGTH 0x200 553 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 554 555 #define PXP_VF_BAR0_START_IGU 0 556 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 557 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 558 559 #define PXP_VF_BAR0_START_DQ 0x3000 560 #define PXP_VF_BAR0_DQ_LENGTH 0x200 561 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 562 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 563 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 564 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 565 566 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 567 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 568 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 569 570 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 571 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 572 573 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 574 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 575 576 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 577 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 578 579 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 580 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 581 582 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 583 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 584 585 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 586 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 587 588 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 589 590 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 591 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 592 593 // ILT Records 594 #define PXP_NUM_ILT_RECORDS_BB 7600 595 #define PXP_NUM_ILT_RECORDS_K2 11000 596 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) 597 598 599 // Host Interface 600 #define PXP_QUEUES_ZONE_MAX_NUM 320 601 602 603 604 605 /*****************/ 606 /* PRM CONSTANTS */ 607 /*****************/ 608 #define PRM_DMA_PAD_BYTES_NUM 2 609 /*****************/ 610 /* SDMs CONSTANTS */ 611 /*****************/ 612 613 614 #define SDM_OP_GEN_TRIG_NONE 0 615 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 616 #define SDM_OP_GEN_TRIG_AGG_INT 2 617 #define SDM_OP_GEN_TRIG_LOADER 4 618 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 619 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 620 621 ///////////////////////////////////////////////////////////// 622 // Completion types 623 ///////////////////////////////////////////////////////////// 624 625 #define SDM_COMP_TYPE_NONE 0 626 #define SDM_COMP_TYPE_WAKE_THREAD 1 627 #define SDM_COMP_TYPE_AGG_INT 2 628 #define SDM_COMP_TYPE_CM 3 // Send direct message to local CM and/or remote CMs. Destinations are defined by vector in CompParams. 629 #define SDM_COMP_TYPE_LOADER 4 630 #define SDM_COMP_TYPE_PXP 5 // Send direct message to PXP (like "internal write" command) to write to remote Storm RAM via remote SDM 631 #define SDM_COMP_TYPE_INDICATE_ERROR 6 // Indicate error per thread 632 #define SDM_COMP_TYPE_RELEASE_THREAD 7 // Obsolete in E5 633 #define SDM_COMP_TYPE_RAM 8 // Write to local RAM as a completion 634 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 // Applicable only for E4 635 636 /******************/ 637 /* PBF CONSTANTS */ 638 /******************/ 639 640 /* Number of PBF command queue lines. Each line is 32B. */ 641 #define PBF_MAX_CMD_LINES 3328 642 643 /* Number of BTB blocks. Each block is 256B. */ 644 #define BTB_MAX_BLOCKS 1440 645 646 /*****************/ 647 /* PRS CONSTANTS */ 648 /*****************/ 649 650 #define PRS_GFT_CAM_LINES_NO_MATCH 31 651 652 /* 653 * Async data KCQ CQE 654 */ 655 struct async_data 656 { 657 __le32 cid /* Context ID of the connection */; 658 __le16 itid /* Task Id of the task (for error that happened on a a task) */; 659 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 660 u8 fw_debug_param /* internal fw debug parameter */; 661 }; 662 663 664 /* 665 * Interrupt coalescing TimeSet 666 */ 667 struct coalescing_timeset 668 { 669 u8 value; 670 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 671 #define COALESCING_TIMESET_TIMESET_SHIFT 0 672 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect */ 673 #define COALESCING_TIMESET_VALID_SHIFT 7 674 }; 675 676 677 struct common_queue_zone 678 { 679 __le16 ring_drv_data_consumer; 680 __le16 reserved; 681 }; 682 683 684 /* 685 * ETH Rx producers data 686 */ 687 struct eth_rx_prod_data 688 { 689 __le16 bd_prod /* BD producer. */; 690 __le16 cqe_prod /* CQE producer. */; 691 }; 692 693 694 struct regpair 695 { 696 __le32 lo /* low word for reg-pair */; 697 __le32 hi /* high word for reg-pair */; 698 }; 699 700 /* 701 * Event Ring VF-PF Channel data 702 */ 703 struct vf_pf_channel_eqe_data 704 { 705 struct regpair msg_addr /* VF-PF message address */; 706 }; 707 708 struct iscsi_eqe_data 709 { 710 __le32 cid /* Context ID of the connection */; 711 __le16 conn_id /* Task Id of the task (for error that happened on a a task) */; 712 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 713 u8 error_pdu_opcode_reserved; 714 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by default=0xFF */ 715 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 716 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_opcode field has valid value */ 717 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 718 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 719 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 720 }; 721 722 /* 723 * RoCE Destroy Event Data 724 */ 725 struct rdma_eqe_destroy_qp 726 { 727 __le32 cid /* Dedicated field RoCE destroy QP event */; 728 u8 reserved[4]; 729 }; 730 731 /* 732 * RDMA Event Data Union 733 */ 734 union rdma_eqe_data 735 { 736 struct regpair async_handle /* Host handle for the Async Completions */; 737 struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */; 738 }; 739 740 /* 741 * Event Ring malicious VF data 742 */ 743 struct malicious_vf_eqe_data 744 { 745 u8 vfId /* Malicious VF ID */; 746 u8 errId /* Malicious VF error */; 747 __le16 reserved[3]; 748 }; 749 750 /* 751 * Event Ring initial cleanup data 752 */ 753 struct initial_cleanup_eqe_data 754 { 755 u8 vfId /* VF ID */; 756 u8 reserved[7]; 757 }; 758 759 /* 760 * Event Data Union 761 */ 762 union event_ring_data 763 { 764 u8 bytes[8] /* Byte Array */; 765 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */; 766 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */; 767 union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */; 768 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */; 769 struct initial_cleanup_eqe_data vf_init_cleanup /* VF Initial Cleanup data */; 770 }; 771 772 773 /* 774 * Event Ring Entry 775 */ 776 struct event_ring_entry 777 { 778 u8 protocol_id /* Event Protocol ID */; 779 u8 opcode /* Event Opcode */; 780 __le16 reserved0 /* Reserved */; 781 __le16 echo /* Echo value from ramrod data on the host */; 782 u8 fw_return_code /* FW return code for SP ramrods */; 783 u8 flags; 784 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */ 785 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 786 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 787 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 788 union event_ring_data data; 789 }; 790 791 792 793 794 795 /* 796 * Multi function mode 797 */ 798 enum mf_mode 799 { 800 ERROR_MODE /* Unsupported mode */, 801 MF_OVLAN /* Multi function based on outer VLAN */, 802 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 803 MAX_MF_MODE 804 }; 805 806 807 /* 808 * Per-protocol connection types 809 */ 810 enum protocol_type 811 { 812 PROTOCOLID_ISCSI /* iSCSI */, 813 PROTOCOLID_FCOE /* FCoE */, 814 PROTOCOLID_ROCE /* RoCE */, 815 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 816 PROTOCOLID_ETH /* Ethernet */, 817 PROTOCOLID_IWARP /* iWARP */, 818 PROTOCOLID_TOE /* TOE */, 819 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 820 PROTOCOLID_COMMON /* ProtocolCommon */, 821 PROTOCOLID_TCP /* TCP */, 822 MAX_PROTOCOL_TYPE 823 }; 824 825 826 827 828 /* 829 * Ustorm Queue Zone 830 */ 831 struct ustorm_eth_queue_zone 832 { 833 struct coalescing_timeset int_coalescing_timeset /* Rx interrupt coalescing TimeSet */; 834 u8 reserved[3]; 835 }; 836 837 838 struct ustorm_queue_zone 839 { 840 struct ustorm_eth_queue_zone eth; 841 struct common_queue_zone common; 842 }; 843 844 845 846 /* 847 * status block structure 848 */ 849 struct cau_pi_entry 850 { 851 __le32 prod; 852 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */ 853 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 854 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is associated with */ 855 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 856 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */ 857 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 858 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */ 859 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 860 }; 861 862 863 /* 864 * status block structure 865 */ 866 struct cau_sb_entry 867 { 868 __le32 data; 869 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */ 870 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 871 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 872 #define CAU_SB_ENTRY_STATE0_SHIFT 24 873 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 874 #define CAU_SB_ENTRY_STATE1_SHIFT 28 875 __le32 params; 876 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated with. */ 877 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 878 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated with. */ 879 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 880 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 881 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 882 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 883 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 884 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 885 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 886 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 887 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 888 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 889 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 890 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones. */ 891 #define CAU_SB_ENTRY_TPH_SHIFT 31 892 }; 893 894 895 /* 896 * core doorbell data 897 */ 898 struct core_db_data 899 { 900 u8 params; 901 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 902 #define CORE_DB_DATA_DEST_SHIFT 0 903 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 904 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 905 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 906 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 907 #define CORE_DB_DATA_RESERVED_MASK 0x1 908 #define CORE_DB_DATA_RESERVED_SHIFT 5 909 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 910 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 911 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 912 __le16 spq_prod; 913 }; 914 915 916 /* 917 * Enum of doorbell aggregative command selection 918 */ 919 enum db_agg_cmd_sel 920 { 921 DB_AGG_CMD_NOP /* No operation */, 922 DB_AGG_CMD_SET /* Set the value */, 923 DB_AGG_CMD_ADD /* Add the value */, 924 DB_AGG_CMD_MAX /* Set max of current and new value */, 925 MAX_DB_AGG_CMD_SEL 926 }; 927 928 929 /* 930 * Enum of doorbell destination 931 */ 932 enum db_dest 933 { 934 DB_DEST_XCM /* TX doorbell to XCM */, 935 DB_DEST_UCM /* RX doorbell to UCM */, 936 DB_DEST_TCM /* RX doorbell to TCM */, 937 DB_NUM_DESTINATIONS, 938 MAX_DB_DEST 939 }; 940 941 942 /* 943 * Enum of doorbell DPM types 944 */ 945 enum db_dpm_type 946 { 947 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 948 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 949 DPM_L2_INLINE /* L2 DPM inline- to PBF, with packet data on doorbell */, 950 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 951 MAX_DB_DPM_TYPE 952 }; 953 954 955 /* 956 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM burst 957 */ 958 struct db_l2_dpm_data 959 { 960 __le16 icid /* internal CID */; 961 __le16 bd_prod /* bd producer value to update */; 962 __le32 params; 963 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 964 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 965 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 966 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 967 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 968 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 969 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */ 970 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 971 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 972 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 973 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */ 974 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 975 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */ 976 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31 977 }; 978 979 980 /* 981 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 982 */ 983 struct db_l2_dpm_sge 984 { 985 struct regpair addr /* Single continuous buffer */; 986 __le16 nbytes /* Number of bytes in this BD. */; 987 __le16 bitfields; 988 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */ 989 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 990 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 991 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 992 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */ 993 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 994 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 995 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 996 __le32 reserved2; 997 }; 998 999 1000 /* 1001 * Structure for doorbell address, in legacy mode 1002 */ 1003 struct db_legacy_addr 1004 { 1005 __le32 addr; 1006 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 1007 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 1008 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */ 1009 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 1010 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 1011 #define DB_LEGACY_ADDR_ICID_SHIFT 5 1012 }; 1013 1014 1015 /* 1016 * Structure for doorbell address, in PWM mode 1017 */ 1018 struct db_pwm_addr 1019 { 1020 __le32 addr; 1021 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 1022 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 1023 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */ 1024 #define DB_PWM_ADDR_OFFSET_SHIFT 3 1025 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 1026 #define DB_PWM_ADDR_WID_SHIFT 10 1027 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 1028 #define DB_PWM_ADDR_DPI_SHIFT 12 1029 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 1030 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 1031 }; 1032 1033 1034 /* 1035 * Parameters to RDMA firmware, passed in EDPM doorbell 1036 */ 1037 struct db_rdma_dpm_params 1038 { 1039 __le32 params; 1040 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 1041 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 1042 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1043 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1044 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */ 1045 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1046 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */ 1047 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1048 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1049 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1050 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */ 1051 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 1052 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1053 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1054 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 1055 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 1056 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 1057 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1058 }; 1059 1060 /* 1061 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a DPM burst 1062 */ 1063 struct db_rdma_dpm_data 1064 { 1065 __le16 icid /* internal CID */; 1066 __le16 prod_val /* aggregated value to update */; 1067 struct db_rdma_dpm_params params /* parametes passed to RDMA firmware */; 1068 }; 1069 1070 1071 1072 /* 1073 * Igu interrupt command 1074 */ 1075 enum igu_int_cmd 1076 { 1077 IGU_INT_ENABLE=0, 1078 IGU_INT_DISABLE=1, 1079 IGU_INT_NOP=2, 1080 IGU_INT_NOP2=3, 1081 MAX_IGU_INT_CMD 1082 }; 1083 1084 1085 /* 1086 * IGU producer or consumer update command 1087 */ 1088 struct igu_prod_cons_update 1089 { 1090 __le32 sb_id_and_flags; 1091 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1092 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1093 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1094 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1095 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1096 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1097 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */ 1098 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1099 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1100 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1101 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1102 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1103 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum command_type_bit) */ 1104 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1105 __le32 reserved1; 1106 }; 1107 1108 1109 /* 1110 * Igu segments access for default status block only 1111 */ 1112 enum igu_seg_access 1113 { 1114 IGU_SEG_ACCESS_REG=0, 1115 IGU_SEG_ACCESS_ATTN=1, 1116 MAX_IGU_SEG_ACCESS 1117 }; 1118 1119 1120 /* 1121 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) 1122 */ 1123 enum l3_type 1124 { 1125 e_l3Type_unknown, 1126 e_l3Type_ipv4, 1127 e_l3Type_ipv6, 1128 MAX_L3_TYPE 1129 }; 1130 1131 1132 /* 1133 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. 1134 */ 1135 enum l4_protocol 1136 { 1137 e_l4Protocol_none, 1138 e_l4Protocol_tcp, 1139 e_l4Protocol_udp, 1140 MAX_L4_PROTOCOL 1141 }; 1142 1143 1144 /* 1145 * Parsing and error flags field. 1146 */ 1147 struct parsing_and_err_flags 1148 { 1149 __le16 flags; 1150 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) (use enum l3_type) */ 1151 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1152 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ 1153 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1154 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4 fragment. */ 1155 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1156 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */ 1157 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1158 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. */ 1159 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1160 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ 1161 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1162 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded. */ 1163 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1164 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 ver mismatch */ 1165 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1166 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation failed. Valid only if L4 checksum was calculated. */ 1167 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1168 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1169 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1170 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* Set if VLAN tag exists in tunnel header. */ 1171 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1172 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ 1173 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1174 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */ 1175 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1176 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ 1177 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1178 }; 1179 1180 1181 /* 1182 * Parsing error flags bitmap. 1183 */ 1184 struct parsing_err_flags 1185 { 1186 __le16 flags; 1187 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */ 1188 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1189 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indication */ 1190 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1191 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indication */ 1192 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1193 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */ 1194 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1195 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output */ 1196 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1197 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output */ 1198 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1199 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len indicates number that is bigger than real packet length 3. tunneling: total-ip-length of the outer header points to offset that is smaller than the one pointed to by the total-ip-len of the inner hdr. */ 1200 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1201 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1202 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1203 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output. for either TCP or UDP */ 1204 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1205 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output */ 1206 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1207 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any reason, like: udp/ipv4 checksum is 0 etc. */ 1208 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1209 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output */ 1210 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1211 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output */ 1212 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1213 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size was over 32 byte */ 1214 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1215 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1216 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1217 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1218 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1219 }; 1220 1221 1222 /* 1223 * Pb context 1224 */ 1225 struct pb_context 1226 { 1227 __le32 crc[4]; 1228 }; 1229 1230 1231 /* 1232 * Concrete Function ID. 1233 */ 1234 struct pxp_concrete_fid 1235 { 1236 __le16 fid; 1237 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1238 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1239 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1240 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1241 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1242 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1243 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1244 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1245 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1246 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1247 }; 1248 1249 1250 /* 1251 * Concrete Function ID. 1252 */ 1253 struct pxp_pretend_concrete_fid 1254 { 1255 __le16 fid; 1256 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1257 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1258 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */ 1259 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1260 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1261 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1262 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1263 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1264 }; 1265 1266 /* 1267 * Function ID. 1268 */ 1269 union pxp_pretend_fid 1270 { 1271 struct pxp_pretend_concrete_fid concrete_fid; 1272 __le16 opaque_fid; 1273 }; 1274 1275 /* 1276 * Pxp Pretend Command Register. 1277 */ 1278 struct pxp_pretend_cmd 1279 { 1280 union pxp_pretend_fid fid; 1281 __le16 control; 1282 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1283 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1284 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1285 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1286 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1287 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1288 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1289 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1290 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1291 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1292 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */ 1293 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1294 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */ 1295 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1296 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */ 1297 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1298 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */ 1299 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1300 }; 1301 1302 1303 1304 1305 /* 1306 * PTT Record in PXP Admin Window. 1307 */ 1308 struct pxp_ptt_entry 1309 { 1310 __le32 offset; 1311 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1312 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1313 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1314 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1315 struct pxp_pretend_cmd pretend; 1316 }; 1317 1318 1319 /* 1320 * VF Zone A Permission Register. 1321 */ 1322 struct pxp_vf_zone_a_permission 1323 { 1324 __le32 control; 1325 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1326 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1327 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1328 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1329 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1330 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1331 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1332 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1333 }; 1334 1335 1336 /* 1337 * Rdif context 1338 */ 1339 struct rdif_task_context 1340 { 1341 __le32 initialRefTag; 1342 __le16 appTagValue; 1343 __le16 appTagMask; 1344 u8 flags0; 1345 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1346 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1347 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1348 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1349 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1350 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1351 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1352 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1353 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1354 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1355 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1356 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1357 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 /* Keep reference tag constant */ 1358 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1359 u8 partialDifData[7]; 1360 __le16 partialCrcValue; 1361 __le16 partialChecksumValue; 1362 __le32 offsetInIO; 1363 __le16 flags1; 1364 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1365 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1366 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1367 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1368 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1369 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1370 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1371 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1372 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1373 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1374 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1375 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1376 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1377 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1378 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1379 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1380 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1381 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1382 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1383 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1384 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1385 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1386 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 /* Forward application tag with mask */ 1387 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1388 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 /* Forward reference tag with mask */ 1389 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1390 __le16 state; 1391 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1392 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1393 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1394 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1395 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1396 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1397 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1398 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1399 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF /* mask for refernce tag handling */ 1400 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1401 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1402 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1403 __le32 reserved2; 1404 }; 1405 1406 1407 1408 /* 1409 * RSS hash type 1410 */ 1411 enum rss_hash_type 1412 { 1413 RSS_HASH_TYPE_DEFAULT=0, 1414 RSS_HASH_TYPE_IPV4=1, 1415 RSS_HASH_TYPE_TCP_IPV4=2, 1416 RSS_HASH_TYPE_IPV6=3, 1417 RSS_HASH_TYPE_TCP_IPV6=4, 1418 RSS_HASH_TYPE_UDP_IPV4=5, 1419 RSS_HASH_TYPE_UDP_IPV6=6, 1420 MAX_RSS_HASH_TYPE 1421 }; 1422 1423 1424 /* 1425 * status block structure 1426 */ 1427 struct status_block 1428 { 1429 __le16 pi_array[PIS_PER_SB]; 1430 __le32 sb_num; 1431 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1432 #define STATUS_BLOCK_SB_NUM_SHIFT 0 1433 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1434 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1435 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1436 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1437 __le32 prod_index; 1438 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1439 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1440 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1441 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1442 }; 1443 1444 1445 /* 1446 * Tdif context 1447 */ 1448 struct tdif_task_context 1449 { 1450 __le32 initialRefTag; 1451 __le16 appTagValue; 1452 __le16 appTagMask; 1453 __le16 partialCrcValueB; 1454 __le16 partialChecksumValueB; 1455 __le16 stateB; 1456 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1457 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1458 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1459 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1460 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1461 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1462 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1463 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1464 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1465 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1466 u8 reserved1; 1467 u8 flags0; 1468 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1469 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1470 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1471 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1472 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1473 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1474 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1475 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1476 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1477 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1478 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1479 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1480 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1481 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1482 __le32 flags1; 1483 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1484 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1485 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1486 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1487 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1488 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1489 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1490 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1491 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1492 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1493 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1494 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1495 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1496 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1497 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1498 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1499 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1500 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1501 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1502 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1503 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1504 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1505 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1506 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1507 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1508 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1509 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1510 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1511 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1512 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1513 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF /* mask for refernce tag handling */ 1514 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1515 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 /* Forward application tag with mask */ 1516 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1517 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 /* Forward reference tag with mask */ 1518 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1519 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 /* Keep reference tag constant */ 1520 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1521 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1522 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1523 __le32 offsetInIOB; 1524 __le16 partialCrcValueA; 1525 __le16 partialChecksumValueA; 1526 __le32 offsetInIOA; 1527 u8 partialDifDataA[8]; 1528 u8 partialDifDataB[8]; 1529 }; 1530 1531 1532 /* 1533 * Timers context 1534 */ 1535 struct timers_context 1536 { 1537 __le32 logical_client_0; 1538 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 */ 1539 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1540 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1541 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1542 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */ 1543 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1544 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */ 1545 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1546 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1547 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1548 __le32 logical_client_1; 1549 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 */ 1550 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1551 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1552 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1553 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */ 1554 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1555 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */ 1556 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1557 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1558 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1559 __le32 logical_client_2; 1560 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 */ 1561 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1562 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1563 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1564 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */ 1565 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1566 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */ 1567 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1568 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1569 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1570 __le32 host_expiration_fields; 1571 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one) */ 1572 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1573 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1574 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1575 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */ 1576 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1577 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1578 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1579 }; 1580 1581 1582 /* 1583 * Enum for next_protocol field of tunnel_parsing_flags 1584 */ 1585 enum tunnel_next_protocol 1586 { 1587 e_unknown=0, 1588 e_l2=1, 1589 e_ipv4=2, 1590 e_ipv6=3, 1591 MAX_TUNNEL_NEXT_PROTOCOL 1592 }; 1593 1594 #endif /* __COMMON_HSI__ */ 1595