Searched refs:MSG_REC (Results 1 – 6 of 6) sorted by relevance
| /illumos-gate/usr/src/uts/sun4/io/px/ |
| H A D | px_pec.c | 164 MSG_REC, (msgcode_t)PCIE_CORR_MSG, -1, in px_pec_msg_add_intr()
176 PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
187 MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, -1, in px_pec_msg_add_intr()
200 PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC, in px_pec_msg_add_intr()
211 MSG_REC, (msgcode_t)PCIE_FATAL_MSG, -1, in px_pec_msg_add_intr()
223 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) { in px_pec_msg_add_intr()
259 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, in px_pec_msg_rem_intr()
264 PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC, in px_pec_msg_rem_intr()
276 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, in px_pec_msg_rem_intr()
281 PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, in px_pec_msg_rem_intr()
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| H A D | px_ioapi.h | 511 MSG_REC = (uint32_t)1, /* PCIe message record */ enumerator
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| H A D | px.c | 648 if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, in px_pwr_setup()
660 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { in px_pwr_setup()
670 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, in px_pwr_setup()
700 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, in px_pwr_teardown()
705 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG); in px_pwr_teardown()
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| H A D | px_msiq.c | 159 if (rec_type == MSG_REC) { in px_msiq_alloc()
241 if (rec_type == MSG_REC) { in px_msiq_alloc_based_on_cpuid()
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| H A D | px_intr.c | 324 case MSG_REC: in px_msiq_intr()
378 if ((rec_type == MSG_REC) && in px_msiq_intr()
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| /illumos-gate/usr/src/uts/sun4u/io/px/ |
| H A D | px_lib4u.c | 1031 msiq_rec_p->msiq_rec_type = MSG_REC; in px_lib_get_msiq_rec()
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