1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_IWARP__ 37 #define __ECORE_HSI_IWARP__ 38 /************************************************************************/ 39 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 40 /************************************************************************/ 41 #include "ecore_hsi_rdma.h" 42 /************************************************************************/ 43 /* Add include to common TCP target */ 44 /************************************************************************/ 45 #include "tcp_common.h" 46 47 /************************************************************************/ 48 /* Add include to common iwarp target for both eCore and protocol iwarp driver */ 49 /************************************************************************/ 50 #include "iwarp_common.h" 51 52 /* 53 * The iwarp storm context of Ystorm 54 */ 55 struct ystorm_iwarp_conn_st_ctx 56 { 57 __le32 reserved[4]; 58 }; 59 60 /* 61 * The iwarp storm context of Pstorm 62 */ 63 struct pstorm_iwarp_conn_st_ctx 64 { 65 __le32 reserved[36]; 66 }; 67 68 /* 69 * The iwarp storm context of Xstorm 70 */ 71 struct xstorm_iwarp_conn_st_ctx 72 { 73 __le32 reserved[44]; 74 }; 75 76 struct e4_xstorm_iwarp_conn_ag_ctx 77 { 78 u8 reserved0 /* cdu_validation */; 79 u8 state /* state */; 80 u8 flags0; 81 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 82 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 83 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */ 84 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 85 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 /* exist_in_qm2 */ 86 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 87 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 88 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 89 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 90 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 91 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */ 92 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 93 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 94 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 95 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 96 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 97 u8 flags1; 98 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 99 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 100 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 101 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 102 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 103 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 104 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 105 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 106 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 107 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 108 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 109 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 110 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 111 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 112 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */ 113 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 114 u8 flags2; 115 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 116 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 117 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 118 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 120 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 121 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 122 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 123 u8 flags3; 124 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 125 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 126 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 127 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 129 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 131 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 132 u8 flags4; 133 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 134 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 135 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 136 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 137 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 138 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 139 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 140 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 141 u8 flags5; 142 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 143 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 144 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 145 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 146 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */ 147 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 148 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 149 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 150 u8 flags6; 151 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */ 152 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 153 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 154 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 155 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 156 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 157 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 158 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 159 u8 flags7; 160 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 161 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 162 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */ 163 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 164 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 165 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 166 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 167 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 168 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 169 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 170 u8 flags8; 171 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 172 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 173 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 174 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 175 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 176 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 177 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 178 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 179 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 180 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 181 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 182 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 183 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 184 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 185 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 186 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 187 u8 flags9; 188 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 189 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 190 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 191 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 192 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 193 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 194 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 195 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 196 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */ 197 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 198 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 199 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 200 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */ 201 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 202 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 203 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 204 u8 flags10; 205 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 206 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 207 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 208 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 209 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 210 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 211 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */ 212 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 213 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 214 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 215 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 216 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 217 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 218 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 219 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */ 220 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 221 u8 flags11; 222 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */ 223 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 224 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 225 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 226 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */ 227 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 228 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 229 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 230 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 231 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 232 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 233 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 234 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 235 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 236 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 237 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 238 u8 flags12; 239 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */ 240 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 241 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 242 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 243 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 244 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 245 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 246 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 247 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 248 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 249 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 250 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 251 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 252 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 253 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 254 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 255 u8 flags13; 256 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */ 257 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 258 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */ 259 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 260 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */ 261 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 262 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */ 263 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 264 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 265 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 266 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */ 267 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 268 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 269 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 270 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 271 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 272 u8 flags14; 273 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 274 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 275 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 276 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 277 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 278 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 279 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 /* bit19 */ 280 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 281 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit20 */ 282 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 283 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit21 */ 284 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 285 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 286 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 287 u8 byte2 /* byte2 */; 288 __le16 physical_q0 /* physical_q0 */; 289 __le16 physical_q1 /* physical_q1 */; 290 __le16 sq_comp_cons /* physical_q2 */; 291 __le16 sq_tx_cons /* word3 */; 292 __le16 sq_prod /* word4 */; 293 __le16 word5 /* word5 */; 294 __le16 conn_dpi /* conn_dpi */; 295 u8 byte3 /* byte3 */; 296 u8 byte4 /* byte4 */; 297 u8 byte5 /* byte5 */; 298 u8 byte6 /* byte6 */; 299 __le32 reg0 /* reg0 */; 300 __le32 reg1 /* reg1 */; 301 __le32 reg2 /* reg2 */; 302 __le32 more_to_send_seq /* reg3 */; 303 __le32 reg4 /* reg4 */; 304 __le32 rewinded_snd_max /* cf_array0 */; 305 __le32 rd_msn /* cf_array1 */; 306 __le16 irq_prod_via_msdm /* word7 */; 307 __le16 irq_cons /* word8 */; 308 __le16 hq_cons_th_or_mpa_data /* word9 */; 309 __le16 hq_cons /* word10 */; 310 __le32 atom_msn /* reg7 */; 311 __le32 orq_cons /* reg8 */; 312 __le32 orq_cons_th /* reg9 */; 313 u8 byte7 /* byte7 */; 314 u8 max_ord /* byte8 */; 315 u8 wqe_data_pad_bytes /* byte9 */; 316 u8 former_hq_prod /* byte10 */; 317 u8 irq_prod_via_msem /* byte11 */; 318 u8 byte12 /* byte12 */; 319 u8 max_pkt_pdu_size_lo /* byte13 */; 320 u8 max_pkt_pdu_size_hi /* byte14 */; 321 u8 byte15 /* byte15 */; 322 u8 e5_reserved /* e5_reserved */; 323 __le16 e5_reserved4 /* word11 */; 324 __le32 reg10 /* reg10 */; 325 __le32 reg11 /* reg11 */; 326 __le32 shared_queue_page_addr_lo /* reg12 */; 327 __le32 shared_queue_page_addr_hi /* reg13 */; 328 __le32 reg14 /* reg14 */; 329 __le32 reg15 /* reg15 */; 330 __le32 reg16 /* reg16 */; 331 __le32 reg17 /* reg17 */; 332 }; 333 334 struct e4_tstorm_iwarp_conn_ag_ctx 335 { 336 u8 reserved0 /* cdu_validation */; 337 u8 state /* state */; 338 u8 flags0; 339 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 340 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 341 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 342 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 343 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 344 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 345 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */ 346 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 347 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 348 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 349 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 350 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 351 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 352 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 353 u8 flags1; 354 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */ 355 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 356 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 /* timer2cf */ 357 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 358 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 359 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 360 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 361 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 362 u8 flags2; 363 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 364 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 365 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 366 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 367 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 368 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 369 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 370 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 371 u8 flags3; 372 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */ 373 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 374 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* cf10 */ 375 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 376 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 377 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 378 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */ 379 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 380 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 /* cf2en */ 381 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 382 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 383 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 384 u8 flags4; 385 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 386 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 387 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 388 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 389 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 390 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 391 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 392 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 393 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 394 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 395 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf9en */ 396 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 397 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf10en */ 398 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 399 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 400 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 401 u8 flags5; 402 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 403 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 404 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 405 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 406 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 407 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 408 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 409 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 410 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 411 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 412 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */ 413 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 414 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 415 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 416 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 417 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 418 __le32 reg0 /* reg0 */; 419 __le32 reg1 /* reg1 */; 420 __le32 unaligned_nxt_seq /* reg2 */; 421 __le32 reg3 /* reg3 */; 422 __le32 reg4 /* reg4 */; 423 __le32 reg5 /* reg5 */; 424 __le32 reg6 /* reg6 */; 425 __le32 reg7 /* reg7 */; 426 __le32 reg8 /* reg8 */; 427 u8 orq_cache_idx /* byte2 */; 428 u8 hq_prod /* byte3 */; 429 __le16 sq_tx_cons_th /* word0 */; 430 u8 orq_prod /* byte4 */; 431 u8 irq_cons /* byte5 */; 432 __le16 sq_tx_cons /* word1 */; 433 __le16 conn_dpi /* conn_dpi */; 434 __le16 rq_prod /* word3 */; 435 __le32 snd_seq /* reg9 */; 436 __le32 last_hq_sequence /* reg10 */; 437 }; 438 439 /* 440 * The iwarp storm context of Tstorm 441 */ 442 struct tstorm_iwarp_conn_st_ctx 443 { 444 __le32 reserved[60]; 445 }; 446 447 /* 448 * The iwarp storm context of Mstorm 449 */ 450 struct mstorm_iwarp_conn_st_ctx 451 { 452 __le32 reserved[32]; 453 }; 454 455 /* 456 * The iwarp storm context of Ustorm 457 */ 458 struct ustorm_iwarp_conn_st_ctx 459 { 460 __le32 reserved[24]; 461 }; 462 463 /* 464 * iwarp connection context 465 */ 466 struct iwarp_conn_context 467 { 468 struct ystorm_iwarp_conn_st_ctx ystorm_st_context /* ystorm storm context */; 469 struct regpair ystorm_st_padding[2] /* padding */; 470 struct pstorm_iwarp_conn_st_ctx pstorm_st_context /* pstorm storm context */; 471 struct regpair pstorm_st_padding[2] /* padding */; 472 struct xstorm_iwarp_conn_st_ctx xstorm_st_context /* xstorm storm context */; 473 struct regpair xstorm_st_padding[2] /* padding */; 474 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 475 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 476 struct timers_context timer_context /* timer context */; 477 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 478 struct tstorm_iwarp_conn_st_ctx tstorm_st_context /* tstorm storm context */; 479 struct regpair tstorm_st_padding[2] /* padding */; 480 struct mstorm_iwarp_conn_st_ctx mstorm_st_context /* mstorm storm context */; 481 struct ustorm_iwarp_conn_st_ctx ustorm_st_context /* ustorm storm context */; 482 }; 483 484 485 /* 486 * iWARP create QP params passed by driver to FW in CreateQP Request Ramrod 487 */ 488 struct iwarp_create_qp_ramrod_data 489 { 490 u8 flags; 491 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 492 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 493 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 494 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 495 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 496 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 497 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 498 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 499 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 500 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 501 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 502 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 503 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3 504 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6 505 u8 reserved1 /* Basic/Enhanced */; 506 __le16 pd; 507 __le16 sq_num_pages; 508 __le16 rq_num_pages; 509 __le32 reserved3[2]; 510 struct regpair qp_handle_for_cqe /* For use in CQEs */; 511 struct rdma_srq_id srq_id; 512 __le32 cq_cid_for_sq /* Cid of the CQ that will be posted from SQ */; 513 __le32 cq_cid_for_rq /* Cid of the CQ that will be posted from RQ */; 514 __le16 dpi; 515 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */; 516 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */; 517 u8 reserved2[6]; 518 }; 519 520 521 /* 522 * iWARP completion queue types 523 */ 524 enum iwarp_eqe_async_opcode 525 { 526 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE /* Async completion oafter TCP 3-way handshake */, 527 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED /* Enhanced MPA reply arrived. Driver should either send RTR or reject */, 528 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE /* MPA Negotiations completed */, 529 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED /* Async completion that indicates to the driver that the CID can be re-used. */, 530 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED /* Async EQE indicating detection of an error/exception on a QP at Firmware */, 531 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE /* Async EQE indicating QP is in Error state. */, 532 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW /* Async EQE indicating CQ, whose handle is sent with this event, has overflowed */, 533 MAX_IWARP_EQE_ASYNC_OPCODE 534 }; 535 536 537 struct iwarp_eqe_data_mpa_async_completion 538 { 539 __le16 ulp_data_len /* On active side, length of ULP Data, from peers MPA Connect Response */; 540 u8 reserved[6]; 541 }; 542 543 544 struct iwarp_eqe_data_tcp_async_completion 545 { 546 __le16 ulp_data_len /* On passive side, length of ULP Data, from peers active MPA Connect Request */; 547 u8 mpa_handshake_mode /* Negotiation type Basic/Enhanced */; 548 u8 reserved[5]; 549 }; 550 551 552 /* 553 * iWARP completion queue types 554 */ 555 enum iwarp_eqe_sync_opcode 556 { 557 IWARP_EVENT_TYPE_TCP_OFFLOAD=11 /* iWARP event queue response after option 2 offload Ramrod */, 558 IWARP_EVENT_TYPE_TCP_ABORT, 559 IWARP_EVENT_TYPE_MPA_OFFLOAD /* Synchronous completion for MPA offload Request */, 560 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 561 IWARP_EVENT_TYPE_CREATE_QP, 562 IWARP_EVENT_TYPE_QUERY_QP, 563 IWARP_EVENT_TYPE_MODIFY_QP, 564 IWARP_EVENT_TYPE_DESTROY_QP, 565 MAX_IWARP_EQE_SYNC_OPCODE 566 }; 567 568 569 /* 570 * iWARP EQE completion status 571 */ 572 enum iwarp_fw_return_code 573 { 574 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET=5 /* Got invalid packet SYN/SYN-ACK */, 575 IWARP_CONN_ERROR_TCP_CONNECTION_RST /* Got RST during offload TCP connection */, 576 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT /* TCP connection setup timed out */, 577 IWARP_CONN_ERROR_MPA_ERROR_REJECT /* Got Reject in MPA reply. */, 578 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER /* Got MPA request with higher version that we support. */, 579 IWARP_CONN_ERROR_MPA_RST /* Got RST during MPA negotiation */, 580 IWARP_CONN_ERROR_MPA_FIN /* Got FIN during MPA negotiation */, 581 IWARP_CONN_ERROR_MPA_RTR_MISMATCH /* RTR mismatch detected when MPA reply arrived. */, 582 IWARP_CONN_ERROR_MPA_INSUF_IRD /* Insufficient IRD on the MPA reply that arrived. */, 583 IWARP_CONN_ERROR_MPA_INVALID_PACKET /* Incoming MPAp acket failed on FW verifications */, 584 IWARP_CONN_ERROR_MPA_LOCAL_ERROR /* Detected an internal error during MPA negotiation. */, 585 IWARP_CONN_ERROR_MPA_TIMEOUT /* MPA negotiation timed out. */, 586 IWARP_CONN_ERROR_MPA_TERMINATE /* Got Terminate during MPA negotiation. */, 587 IWARP_QP_IN_ERROR_GOOD_CLOSE /* LLP connection was closed gracefully - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */, 588 IWARP_QP_IN_ERROR_BAD_CLOSE /* LLP Connection was closed abortively - Used for async IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE */, 589 IWARP_EXCEPTION_DETECTED_LLP_CLOSED /* LLP has been disociated from the QP, although the TCP connection may not be closed yet - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 590 IWARP_EXCEPTION_DETECTED_LLP_RESET /* LLP has Reset (either because of an RST, or a bad-close condition) - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 591 IWARP_EXCEPTION_DETECTED_IRQ_FULL /* Peer sent more outstanding Read Requests than IRD - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 592 IWARP_EXCEPTION_DETECTED_RQ_EMPTY /* SEND request received with RQ empty - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 593 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT /* TCP Retransmissions timed out - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 594 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR /* Peers Remote Access caused error */, 595 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW /* CQ overflow detected */, 596 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC /* Local catastrophic error detected - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 597 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR /* Local Access error detected while responding - Used for async IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED */, 598 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR /* An operation/protocol error caused by Remote Consumer */, 599 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED /* Peer sent a TERMINATE message */, 600 MAX_IWARP_FW_RETURN_CODE 601 }; 602 603 604 /* 605 * unaligned opaque data received from LL2 606 */ 607 struct iwarp_init_func_params 608 { 609 u8 ll2_ooo_q_index /* LL2 OOO queue id. The unaligned queue id will be + 1 */; 610 u8 reserved1[7]; 611 }; 612 613 614 /* 615 * iwarp func init ramrod data 616 */ 617 struct iwarp_init_func_ramrod_data 618 { 619 struct rdma_init_func_ramrod_data rdma; 620 struct tcp_init_params tcp; 621 struct iwarp_init_func_params iwarp; 622 }; 623 624 625 /* 626 * iWARP QP - possible states to transition to 627 */ 628 enum iwarp_modify_qp_new_state_type 629 { 630 IWARP_MODIFY_QP_STATE_CLOSING=1 /* graceful close */, 631 IWARP_MODIFY_QP_STATE_ERROR=2 /* abortive close, if LLP connection still exists */, 632 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 633 }; 634 635 636 /* 637 * iwarp modify qp responder ramrod data 638 */ 639 struct iwarp_modify_qp_ramrod_data 640 { 641 __le16 transition_to_state; 642 __le16 flags; 643 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 644 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 645 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 646 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 647 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 648 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 649 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 /* change QP state as per transition_to_state field */ 650 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 651 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 /* If set, the rdma_rd/wr/atomic_en should be updated */ 652 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 653 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF 654 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5 655 __le32 reserved3[3]; 656 __le32 reserved4[8]; 657 }; 658 659 660 /* 661 * MPA params for Enhanced mode 662 */ 663 struct mpa_rq_params 664 { 665 __le32 ird; 666 __le32 ord; 667 }; 668 669 /* 670 * MPA host Address-Len for private data 671 */ 672 struct mpa_ulp_buffer 673 { 674 struct regpair addr; 675 __le16 len; 676 __le16 reserved[3]; 677 }; 678 679 /* 680 * iWARP MPA offload params common to Basic and Enhanced modes 681 */ 682 struct mpa_outgoing_params 683 { 684 u8 crc_needed; 685 u8 reject /* Valid only for passive side. */; 686 u8 reserved[6]; 687 struct mpa_rq_params out_rq; 688 struct mpa_ulp_buffer outgoing_ulp_buffer /* ULP buffer populated by the host */; 689 }; 690 691 /* 692 * iWARP MPA offload params passed by driver to FW in MPA Offload Request Ramrod 693 */ 694 struct iwarp_mpa_offload_ramrod_data 695 { 696 struct mpa_outgoing_params common; 697 __le32 tcp_cid; 698 u8 mode /* Basic/Enhanced */; 699 u8 tcp_connect_side /* Passive/Active. use enum tcp_connect_mode */; 700 u8 rtr_pref; 701 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 /* (use enum mpa_rtr_type) */ 702 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 703 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 704 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 705 u8 reserved2; 706 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA reply */; 707 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */; 708 struct regpair handle_for_async /* a host cookie that will be echoed back with in every qp-specific async EQE */; 709 struct regpair shared_queue_addr /* Address of shared queue adress that consist of SQ/RQ and FW internal queues (IRQ/ORQ/HQ) */; 710 u8 stats_counter_id /* Statistics counter ID to use */; 711 u8 reserved3[15]; 712 }; 713 714 715 /* 716 * iWARP TCP connection offload params passed by driver to FW 717 */ 718 struct iwarp_offload_params 719 { 720 struct mpa_ulp_buffer incoming_ulp_buffer /* host buffer for placing the incoming MPA request */; 721 struct regpair async_eqe_output_buf /* host buffer for async tcp/mpa completion information - must have space for at least 8 bytes */; 722 struct regpair handle_for_async /* host handle that will be echoed back with in every qp-specific async EQE */; 723 __le16 physical_q0 /* Physical QM queue to be tied to logical Q0 */; 724 __le16 physical_q1 /* Physical QM queue to be tied to logical Q1 */; 725 u8 stats_counter_id /* Statistics counter ID to use */; 726 u8 mpa_mode /* Basic/Enahnced. Used for a verification for incoming MPA request */; 727 u8 reserved[10]; 728 }; 729 730 731 /* 732 * iWARP query QP output params 733 */ 734 struct iwarp_query_qp_output_params 735 { 736 __le32 flags; 737 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 738 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 739 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 740 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 741 u8 reserved1[4] /* 64 bit alignment */; 742 }; 743 744 745 /* 746 * iWARP query QP ramrod data 747 */ 748 struct iwarp_query_qp_ramrod_data 749 { 750 struct regpair output_params_addr; 751 }; 752 753 754 /* 755 * iWARP Ramrod Command IDs 756 */ 757 enum iwarp_ramrod_cmd_id 758 { 759 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD=11 /* iWARP TCP connection offload ramrod */, 760 IWARP_RAMROD_CMD_ID_TCP_ABORT /* Abort TCP connection without changing the QP state. */, 761 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD /* iWARP MPA offload ramrod */, 762 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 763 IWARP_RAMROD_CMD_ID_CREATE_QP, 764 IWARP_RAMROD_CMD_ID_QUERY_QP, 765 IWARP_RAMROD_CMD_ID_MODIFY_QP, 766 IWARP_RAMROD_CMD_ID_DESTROY_QP, 767 MAX_IWARP_RAMROD_CMD_ID 768 }; 769 770 771 /* 772 * Per PF iWARP retransmit path statistics 773 */ 774 struct iwarp_rxmit_stats_drv 775 { 776 struct regpair tx_go_to_slow_start_event_cnt /* Number of times slow start event occurred */; 777 struct regpair tx_fast_retransmit_event_cnt /* Number of times fast retransmit event occurred */; 778 }; 779 780 781 /* 782 * iWARP and TCP connection offload params passed by driver to FW in iWARP offload ramrod 783 */ 784 struct iwarp_tcp_offload_ramrod_data 785 { 786 struct iwarp_offload_params iwarp /* iWARP connection offload params */; 787 struct tcp_offload_params_opt2 tcp /* tcp offload params */; 788 }; 789 790 791 /* 792 * iWARP MPA negotiation types 793 */ 794 enum mpa_negotiation_mode 795 { 796 MPA_NEGOTIATION_TYPE_BASIC=1, 797 MPA_NEGOTIATION_TYPE_ENHANCED=2, 798 MAX_MPA_NEGOTIATION_MODE 799 }; 800 801 802 803 804 /* 805 * iWARP MPA Enhanced mode RTR types 806 */ 807 enum mpa_rtr_type 808 { 809 MPA_RTR_TYPE_NONE=0 /* No RTR type */, 810 MPA_RTR_TYPE_ZERO_SEND=1, 811 MPA_RTR_TYPE_ZERO_WRITE=2, 812 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE=3, 813 MPA_RTR_TYPE_ZERO_READ=4, 814 MPA_RTR_TYPE_ZERO_SEND_AND_READ=5, 815 MPA_RTR_TYPE_ZERO_WRITE_AND_READ=6, 816 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ=7, 817 MAX_MPA_RTR_TYPE 818 }; 819 820 821 822 823 824 825 /* 826 * unaligned opaque data received from LL2 827 */ 828 struct unaligned_opaque_data 829 { 830 __le16 first_mpa_offset /* offset of first MPA byte that should be processed */; 831 u8 tcp_payload_offset /* offset of first the byte that comes after the last byte of the TCP Hdr */; 832 u8 flags; 833 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 /* packet reached window right edge */ 834 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 835 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 /* Indication that the connection is closed. Clean all connecitons database. */ 836 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 837 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 838 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 839 __le32 cid; 840 }; 841 842 843 844 845 846 struct e4_mstorm_iwarp_conn_ag_ctx 847 { 848 u8 reserved /* cdu_validation */; 849 u8 state /* state */; 850 u8 flags0; 851 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 852 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 853 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 854 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 855 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 856 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 857 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 858 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 859 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 860 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 861 u8 flags1; 862 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 863 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 864 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 865 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 866 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 867 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 868 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 869 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 870 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 871 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 872 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 873 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 874 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 875 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 876 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 877 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 878 __le16 rcq_cons /* word0 */; 879 __le16 rcq_cons_th /* word1 */; 880 __le32 reg0 /* reg0 */; 881 __le32 reg1 /* reg1 */; 882 }; 883 884 885 886 struct e4_ustorm_iwarp_conn_ag_ctx 887 { 888 u8 reserved /* cdu_validation */; 889 u8 byte1 /* state */; 890 u8 flags0; 891 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 892 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 893 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 894 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 895 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 896 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 897 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 898 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 899 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 900 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 901 u8 flags1; 902 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 903 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 904 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 905 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 906 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 907 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 908 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 909 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 910 u8 flags2; 911 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 912 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 913 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 914 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 915 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 916 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 917 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 918 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 919 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 920 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 921 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 922 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 923 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 924 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 925 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 926 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 927 u8 flags3; 928 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 929 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 930 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 931 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 932 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 933 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 934 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 935 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 936 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 937 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 938 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 939 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 940 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 941 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 942 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 943 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 944 u8 byte2 /* byte2 */; 945 u8 byte3 /* byte3 */; 946 __le16 word0 /* conn_dpi */; 947 __le16 word1 /* word1 */; 948 __le32 cq_cons /* reg0 */; 949 __le32 cq_se_prod /* reg1 */; 950 __le32 cq_prod /* reg2 */; 951 __le32 reg3 /* reg3 */; 952 __le16 word2 /* word2 */; 953 __le16 word3 /* word3 */; 954 }; 955 956 957 958 struct e4_ystorm_iwarp_conn_ag_ctx 959 { 960 u8 byte0 /* cdu_validation */; 961 u8 byte1 /* state */; 962 u8 flags0; 963 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 964 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 965 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 966 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 967 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 968 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 969 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 970 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 971 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 972 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 973 u8 flags1; 974 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 975 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 976 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 977 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 978 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 979 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 980 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 981 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 982 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 983 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 984 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 985 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 986 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 987 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 988 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 989 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 990 u8 byte2 /* byte2 */; 991 u8 byte3 /* byte3 */; 992 __le16 word0 /* word0 */; 993 __le32 reg0 /* reg0 */; 994 __le32 reg1 /* reg1 */; 995 __le16 word1 /* word1 */; 996 __le16 word2 /* word2 */; 997 __le16 word3 /* word3 */; 998 __le16 word4 /* word4 */; 999 __le32 reg2 /* reg2 */; 1000 __le32 reg3 /* reg3 */; 1001 }; 1002 1003 1004 struct e5_mstorm_iwarp_conn_ag_ctx 1005 { 1006 u8 reserved /* cdu_validation */; 1007 u8 state_and_core_id /* state_and_core_id */; 1008 u8 flags0; 1009 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1010 #define E5_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1011 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1012 #define E5_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1013 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */ 1014 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 1015 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1016 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1017 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1018 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1019 u8 flags1; 1020 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 /* cf0en */ 1021 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 1022 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1023 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1024 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1025 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1026 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1027 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1028 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1029 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1030 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1031 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1032 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 /* rule3en */ 1033 #define E5_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 1034 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1035 #define E5_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1036 __le16 rcq_cons /* word0 */; 1037 __le16 rcq_cons_th /* word1 */; 1038 __le32 reg0 /* reg0 */; 1039 __le32 reg1 /* reg1 */; 1040 }; 1041 1042 1043 struct e5_tstorm_iwarp_conn_ag_ctx 1044 { 1045 u8 reserved0 /* cdu_validation */; 1046 u8 state_and_core_id /* state_and_core_id */; 1047 u8 flags0; 1048 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1049 #define E5_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1050 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1051 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1052 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1053 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 1054 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit3 */ 1055 #define E5_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 1056 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1057 #define E5_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 1058 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 1059 #define E5_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 1060 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1061 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 1062 u8 flags1; 1063 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */ 1064 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 1065 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* timer2cf */ 1066 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 1067 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 1068 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 1069 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1070 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 1071 u8 flags2; 1072 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1073 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 1074 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1075 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 1076 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1077 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 1078 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1079 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 1080 u8 flags3; 1081 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */ 1082 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1083 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1084 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 2 1085 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1086 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 1087 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 /* cf1en */ 1088 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 1089 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 /* cf2en */ 1090 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 1091 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 1092 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 1093 u8 flags4; 1094 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1095 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 1096 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1097 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 1098 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1099 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 1100 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1101 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 1102 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1103 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 1104 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf9en */ 1105 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 1106 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1107 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 6 1108 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1109 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 1110 u8 flags5; 1111 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1112 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 1113 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1114 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 1115 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1116 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 1117 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1118 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 1119 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1120 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 1121 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 /* rule6en */ 1122 #define E5_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 1123 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1124 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 1125 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1126 #define E5_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 1127 u8 flags6; 1128 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1129 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1130 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1131 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1132 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1133 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1134 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1135 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1136 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1137 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1138 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1139 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1140 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1141 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1142 u8 orq_cache_idx /* byte2 */; 1143 __le16 sq_tx_cons_th /* word0 */; 1144 __le32 reg0 /* reg0 */; 1145 __le32 reg1 /* reg1 */; 1146 __le32 unaligned_nxt_seq /* reg2 */; 1147 __le32 reg3 /* reg3 */; 1148 __le32 reg4 /* reg4 */; 1149 __le32 reg5 /* reg5 */; 1150 __le32 reg6 /* reg6 */; 1151 __le32 reg7 /* reg7 */; 1152 __le32 reg8 /* reg8 */; 1153 u8 hq_prod /* byte3 */; 1154 u8 orq_prod /* byte4 */; 1155 u8 irq_cons /* byte5 */; 1156 u8 e4_reserved8 /* byte6 */; 1157 __le16 sq_tx_cons /* word1 */; 1158 __le16 conn_dpi /* conn_dpi */; 1159 __le32 snd_seq /* reg9 */; 1160 __le16 rq_prod /* word3 */; 1161 __le16 e4_reserved9 /* word4 */; 1162 }; 1163 1164 1165 struct e5_ustorm_iwarp_conn_ag_ctx 1166 { 1167 u8 reserved /* cdu_validation */; 1168 u8 byte1 /* state_and_core_id */; 1169 u8 flags0; 1170 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1171 #define E5_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1172 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1173 #define E5_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1174 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1175 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1176 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1177 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1178 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1179 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1180 u8 flags1; 1181 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1182 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 1183 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1184 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1185 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1186 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1187 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1188 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 1189 u8 flags2; 1190 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1191 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1192 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1193 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1194 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1195 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1196 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1197 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 1198 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1199 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1200 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1201 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1202 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1203 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 1204 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1205 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1206 u8 flags3; 1207 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1208 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 1209 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1210 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 1211 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1212 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 1213 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1214 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 1215 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1216 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 1217 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1218 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 1219 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1220 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 1221 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1222 #define E5_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 1223 u8 flags4; 1224 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1225 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1226 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1227 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1228 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1229 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1230 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1231 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1232 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1233 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1234 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1235 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1236 u8 byte2 /* byte2 */; 1237 __le16 word0 /* conn_dpi */; 1238 __le16 word1 /* word1 */; 1239 __le32 cq_cons /* reg0 */; 1240 __le32 cq_se_prod /* reg1 */; 1241 __le32 cq_prod /* reg2 */; 1242 __le32 reg3 /* reg3 */; 1243 __le16 word2 /* word2 */; 1244 __le16 word3 /* word3 */; 1245 }; 1246 1247 1248 struct e5_xstorm_iwarp_conn_ag_ctx 1249 { 1250 u8 reserved0 /* cdu_validation */; 1251 u8 state_and_core_id /* state_and_core_id */; 1252 u8 flags0; 1253 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1254 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1255 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */ 1256 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 1257 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */ 1258 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED1_SHIFT 2 1259 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1260 #define E5_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1261 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1262 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 1263 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */ 1264 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 1265 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1266 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 1267 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1268 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 1269 u8 flags1; 1270 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1271 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 1272 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1273 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 1274 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1275 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 1276 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1277 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 1278 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1279 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 1280 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1281 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 1282 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1283 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 1284 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 /* bit15 */ 1285 #define E5_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 1286 u8 flags2; 1287 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1288 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 1289 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1290 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 1291 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1292 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 1293 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 1294 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 1295 u8 flags3; 1296 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1297 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 1298 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1299 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 1300 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1301 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 1302 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1303 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 1304 u8 flags4; 1305 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1306 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 1307 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1308 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 1309 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1310 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 1311 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1312 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 1313 u8 flags5; 1314 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1315 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 1316 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1317 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 1318 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */ 1319 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 1320 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1321 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 1322 u8 flags6; 1323 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */ 1324 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 1325 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1326 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 1327 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1328 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 1329 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */ 1330 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 1331 u8 flags7; 1332 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 1333 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1334 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */ 1335 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 1336 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1337 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1338 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1339 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 1340 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1341 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 1342 u8 flags8; 1343 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1344 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 1345 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 1346 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 1347 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1348 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 1349 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1350 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 1351 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1352 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 1353 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1354 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 1355 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1356 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 1357 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1358 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 1359 u8 flags9; 1360 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1361 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 1362 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1363 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 1364 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1365 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 1366 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1367 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 1368 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf14en */ 1369 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 1370 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1371 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 1372 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 /* cf16en */ 1373 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 1374 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1375 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 1376 u8 flags10; 1377 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1378 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 1379 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 /* cf19en */ 1380 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 1381 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1382 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 1383 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 /* cf21en */ 1384 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 1385 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1386 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1387 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1388 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 1389 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1390 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 1391 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 /* rule1en */ 1392 #define E5_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 1393 u8 flags11; 1394 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 /* rule2en */ 1395 #define E5_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 1396 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1397 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 1398 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* rule4en */ 1399 #define E5_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 1400 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1401 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 1402 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1403 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 1404 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1405 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 1406 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1407 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1408 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1409 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 1410 u8 flags12; 1411 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule10en */ 1412 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 1413 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1414 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 1415 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1416 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1417 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1418 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1419 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1420 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 1421 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1422 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 1423 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1424 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 1425 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1426 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 1427 u8 flags13; 1428 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 /* rule18en */ 1429 #define E5_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 1430 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule19en */ 1431 #define E5_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 1432 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 /* rule20en */ 1433 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 1434 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 /* rule21en */ 1435 #define E5_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 1436 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1437 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1438 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 /* rule23en */ 1439 #define E5_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 1440 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1441 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1442 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1443 #define E5_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1444 u8 flags14; 1445 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1446 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 1447 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1448 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 1449 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1450 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1451 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1452 #define E5_XSTORM_IWARP_CONN_AG_CTX_BIT20_SHIFT 4 1453 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1454 #define E5_XSTORM_IWARP_CONN_AG_CTX_RDMA_EDPM_ENABLE_SHIFT 5 1455 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1456 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 1457 u8 byte2 /* byte2 */; 1458 __le16 physical_q0 /* physical_q0 */; 1459 __le16 physical_q1 /* physical_q1 */; 1460 __le16 sq_comp_cons /* physical_q2 */; 1461 __le16 sq_tx_cons /* word3 */; 1462 __le16 sq_prod /* word4 */; 1463 __le16 word5 /* word5 */; 1464 __le16 conn_dpi /* conn_dpi */; 1465 u8 byte3 /* byte3 */; 1466 u8 byte4 /* byte4 */; 1467 u8 byte5 /* byte5 */; 1468 u8 byte6 /* byte6 */; 1469 __le32 reg0 /* reg0 */; 1470 __le32 reg1 /* reg1 */; 1471 __le32 reg2 /* reg2 */; 1472 __le32 more_to_send_seq /* reg3 */; 1473 __le32 reg4 /* reg4 */; 1474 __le32 rewinded_snd_max /* cf_array0 */; 1475 __le32 rd_msn /* cf_array1 */; 1476 u8 flags15; 1477 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1478 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1479 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1480 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1481 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1482 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1483 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1484 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1485 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1486 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1487 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1488 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1489 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1490 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1491 u8 byte7 /* byte7 */; 1492 __le16 irq_prod_via_msdm /* word7 */; 1493 __le16 irq_cons /* word8 */; 1494 __le16 hq_cons_th_or_mpa_data /* word9 */; 1495 __le16 hq_cons /* word10 */; 1496 __le16 tx_rdma_edpm_usg_cnt /* word11 */; 1497 __le32 atom_msn /* reg7 */; 1498 __le32 orq_cons /* reg8 */; 1499 __le32 orq_cons_th /* reg9 */; 1500 u8 max_ord /* byte8 */; 1501 u8 wqe_data_pad_bytes /* byte9 */; 1502 u8 former_hq_prod /* byte10 */; 1503 u8 irq_prod_via_msem /* byte11 */; 1504 u8 byte12 /* byte12 */; 1505 u8 max_pkt_pdu_size_lo /* byte13 */; 1506 u8 max_pkt_pdu_size_hi /* byte14 */; 1507 u8 byte15 /* byte15 */; 1508 __le32 reg10 /* reg10 */; 1509 __le32 reg11 /* reg11 */; 1510 __le32 reg12 /* reg12 */; 1511 __le32 shared_queue_page_addr_lo /* reg13 */; 1512 __le32 shared_queue_page_addr_hi /* reg14 */; 1513 __le32 reg15 /* reg15 */; 1514 __le32 reg16 /* reg16 */; 1515 __le32 reg17 /* reg17 */; 1516 }; 1517 1518 1519 struct e5_ystorm_iwarp_conn_ag_ctx 1520 { 1521 u8 byte0 /* cdu_validation */; 1522 u8 byte1 /* state_and_core_id */; 1523 u8 flags0; 1524 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1525 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 1526 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1527 #define E5_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 1528 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1529 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 1530 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1531 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 1532 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1533 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 1534 u8 flags1; 1535 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1536 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 1537 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1538 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 1539 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1540 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 1541 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1542 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 1543 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1544 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 1545 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1546 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 1547 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1548 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 1549 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1550 #define E5_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 1551 u8 byte2 /* byte2 */; 1552 u8 byte3 /* byte3 */; 1553 __le16 word0 /* word0 */; 1554 __le32 reg0 /* reg0 */; 1555 __le32 reg1 /* reg1 */; 1556 __le16 word1 /* word1 */; 1557 __le16 word2 /* word2 */; 1558 __le16 word3 /* word3 */; 1559 __le16 word4 /* word4 */; 1560 __le32 reg2 /* reg2 */; 1561 __le32 reg3 /* reg3 */; 1562 }; 1563 1564 #endif /* __ECORE_HSI_IWARP__ */ 1565