1 /*-
2 * Copyright (c) 2017-2018 QCM Technologies.
3 * Copyright (c) 2017-2018 Semihalf.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include "opt_platform.h"
29
30 #include <sys/param.h>
31 #include <sys/endian.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/conf.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/mbuf.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/rman.h>
42 #include <machine/bus.h>
43
44 #include <vm/vm.h>
45 #include <vm/pmap.h>
46
47 #include <dev/iicbus/iiconf.h>
48 #include <dev/iicbus/iicbus.h>
49 #include "iicbus_if.h"
50
51 #include "opal.h"
52
53 #ifdef FDT
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56 #endif
57
58 struct opal_i2c_softc
59 {
60 device_t dev;
61 device_t iicbus;
62 uint32_t opal_id;
63 struct mtx sc_mtx;
64 };
65
66 /* OPAL I2C request */
67 struct opal_i2c_request {
68 uint8_t type;
69 #define OPAL_I2C_RAW_READ 0
70 #define OPAL_I2C_RAW_WRITE 1
71 #define OPAL_I2C_SM_READ 2
72 #define OPAL_I2C_SM_WRITE 3
73 uint8_t flags;
74 uint8_t subaddr_sz; /* Max 4 */
75 uint8_t reserved;
76 uint16_t addr; /* 7 or 10 bit address */
77 uint16_t reserved2;
78 uint32_t subaddr; /* Sub-address if any */
79 uint32_t size; /* Data size */
80 uint64_t buffer_pa; /* Buffer real address */
81 };
82
83 static int opal_i2c_attach(device_t);
84 static int opal_i2c_callback(device_t, int, caddr_t);
85 static int opal_i2c_probe(device_t);
86 static int opal_i2c_transfer(device_t, struct iic_msg *, uint32_t);
87 static int i2c_opal_send_request(uint32_t, struct opal_i2c_request *);
88 static phandle_t opal_i2c_get_node(device_t bus, device_t dev);
89
90 static device_method_t opal_i2c_methods[] = {
91 /* Device interface */
92 DEVMETHOD(device_probe, opal_i2c_probe),
93 DEVMETHOD(device_attach, opal_i2c_attach),
94
95 /* iicbus interface */
96 DEVMETHOD(iicbus_callback, opal_i2c_callback),
97 DEVMETHOD(iicbus_transfer, opal_i2c_transfer),
98 DEVMETHOD(ofw_bus_get_node, opal_i2c_get_node),
99 DEVMETHOD_END
100 };
101
102 #define I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
103 #define I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
104 #define I2C_LOCK_INIT(_sc) \
105 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
106 "i2c", MTX_DEF)
107
108 static driver_t opal_i2c_driver = {
109 "iichb",
110 opal_i2c_methods,
111 sizeof(struct opal_i2c_softc),
112 };
113
114 static int
opal_i2c_probe(device_t dev)115 opal_i2c_probe(device_t dev)
116 {
117
118 if (!(ofw_bus_is_compatible(dev, "ibm,opal-i2c")))
119 return (ENXIO);
120
121 device_set_desc(dev, "opal-i2c");
122
123 return (0);
124 }
125
126 static int
opal_i2c_attach(device_t dev)127 opal_i2c_attach(device_t dev)
128 {
129 struct opal_i2c_softc *sc;
130 int len;
131
132 sc = device_get_softc(dev);
133 sc->dev = dev;
134
135 len = OF_getproplen(ofw_bus_get_node(dev), "ibm,opal-id");
136 if (len <= 0)
137 return (EINVAL);
138 OF_getencprop(ofw_bus_get_node(dev), "ibm,opal-id", &sc->opal_id, len);
139
140 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
141 device_printf(dev, "could not allocate iicbus instance\n");
142 return (EINVAL);
143 }
144
145 I2C_LOCK_INIT(sc);
146
147 return (bus_generic_attach(dev));
148 }
149
150 static int
opal_get_async_rc(struct opal_msg msg)151 opal_get_async_rc(struct opal_msg msg)
152 {
153 if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
154 return OPAL_PARAMETER;
155 else
156 return htobe64(msg.params[1]);
157 }
158
159 static int
i2c_opal_send_request(uint32_t bus_id,struct opal_i2c_request * req)160 i2c_opal_send_request(uint32_t bus_id, struct opal_i2c_request *req)
161 {
162 struct opal_msg msg;
163 uint64_t token;
164 int rc;
165
166 token = opal_alloc_async_token();
167
168 memset(&msg, 0, sizeof(msg));
169
170 rc = opal_call(OPAL_I2C_REQUEST, token, bus_id,
171 vtophys(req));
172 if (rc != OPAL_ASYNC_COMPLETION)
173 goto out;
174
175 rc = opal_wait_completion(&msg, sizeof(msg), token);
176
177 if (rc != OPAL_SUCCESS)
178 goto out;
179
180 rc = opal_get_async_rc(msg);
181
182 out:
183 opal_free_async_token(token);
184
185 return (rc);
186 }
187
188 static int
opal_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)189 opal_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
190 {
191 struct opal_i2c_softc *sc;
192 int i, err = 0;
193 struct opal_i2c_request req;
194
195 sc = device_get_softc(dev);
196
197 memset(&req, 0, sizeof(req));
198
199 I2C_LOCK(sc);
200 for (i = 0; i < nmsgs; i++) {
201 req.type = (msgs[i].flags & IIC_M_RD) ?
202 OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE;
203 req.addr = htobe16(msgs[i].slave >> 1);
204 req.size = htobe32(msgs[i].len);
205 req.buffer_pa = htobe64(pmap_kextract((uint64_t)msgs[i].buf));
206
207 err = i2c_opal_send_request(sc->opal_id, &req);
208 }
209 I2C_UNLOCK(sc);
210
211 return (err);
212 }
213
214 static int
opal_i2c_callback(device_t dev,int index,caddr_t data)215 opal_i2c_callback(device_t dev, int index, caddr_t data)
216 {
217 int error = 0;
218
219 switch (index) {
220 case IIC_REQUEST_BUS:
221 break;
222
223 case IIC_RELEASE_BUS:
224 break;
225
226 default:
227 error = EINVAL;
228 }
229
230 return (error);
231 }
232
233 static phandle_t
opal_i2c_get_node(device_t bus,device_t dev)234 opal_i2c_get_node(device_t bus, device_t dev)
235 {
236
237 /* Share controller node with iibus device. */
238 return (ofw_bus_get_node(bus));
239 }
240
241 DRIVER_MODULE(opal_i2c, opal_i2cm, opal_i2c_driver, NULL, NULL);
242 DRIVER_MODULE(iicbus, opal_i2c, iicbus_driver, NULL, NULL);
243 MODULE_DEPEND(opal_i2c, iicbus, 1, 1, 1);
244