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Searched refs:sra (Results 1 – 25 of 63) sorted by relevance

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/freebsd/sys/contrib/openzfs/module/zfs/
H A Dbpobj.c954 struct space_range_arg *sra = arg; in space_range_cb() local
956 if (BP_GET_LOGICAL_BIRTH(bp) > sra->mintxg && in space_range_cb()
957 BP_GET_LOGICAL_BIRTH(bp) <= sra->maxtxg) { in space_range_cb()
958 if (dsl_pool_sync_context(spa_get_dsl(sra->spa))) in space_range_cb()
959 sra->used += bp_get_dsize_sync(sra->spa, bp); in space_range_cb()
961 sra->used += bp_get_dsize(sra->spa, bp); in space_range_cb()
962 sra->comp += BP_GET_PSIZE(bp); in space_range_cb()
963 sra->uncomp += BP_GET_UCSIZE(bp); in space_range_cb()
995 struct space_range_arg sra = { 0 }; in bpobj_space_range() local
1007 sra.spa = dmu_objset_spa(bpo->bpo_os); in bpobj_space_range()
[all …]
/freebsd/sys/contrib/openzfs/config/
H A Dalways-compiler-options.m4308 dnl # Check if cc supports -fno-ipa-sra option.
311 AC_MSG_CHECKING([whether $CC supports -fno-ipa-sra])
314 CFLAGS="$CFLAGS -Werror -fno-ipa-sra"
317 NO_IPA_SRA=-fno-ipa-sra
329 dnl # Check if kernel cc supports -fno-ipa-sra option.
332 AC_MSG_CHECKING([whether $KERNEL_CC supports -fno-ipa-sra])
337 CFLAGS="$CFLAGS -Werror -fno-ipa-sra"
347 KERNEL_NO_IPA_SRA=-fno-ipa-sra
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td228 defm SAR: ShiftRotate<"sar", MRM7r, MRM7m, sra, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>;
681 defm SARX : ShiftX_Pats<sra>;
688 defm SARX : ShiftX_Pats<sra, "_EVEX">;
/freebsd/lib/libtelnet/
H A DMakefile17 SRCS+= encrypt.c auth.c enc_des.c sra.c pk.c
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td67 defm SHR_S : BinaryInt<sra, "shr_s", 0x75, 0x87>;
98 def : Pat<(sra I32:$lhs, (and I32:$rhs, 31)), (SHR_S_I32 I32:$lhs, I32:$rhs)>;
101 def : Pat<(sra I64:$lhs, (and I64:$rhs, 63)), (SHR_S_I64 I64:$lhs, I64:$rhs)>;
/freebsd/crypto/openssl/crypto/bn/asm/
H A Ds390x.S31 sra %r4,2 // cnt=len/4
140 sra %r4,2 // cnt=len/4
269 sra %r5,2 // len/4, use sra because it sets condition code
323 sra %r5,2 // len/4, use sra because it sets condition code
H A Dsparcv8plus.S178 sra %o2,%g0,%o2 ! signx %o2
280 sra %o2,%g0,%o2 ! signx %o2
368 sra %o2,%g0,%o2 ! signx %o2
473 sra %o3,%g0,%o3 ! signx %o3
551 sra %o3,%g0,%o3 ! signx %o3
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td95 defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td782 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
1233 def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
1235 def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1370 def : MipsInstAlias<"sra $rd, $rt, $rs",
1376 def : MipsInstAlias<"sra $rd, $rt",
1382 def : MipsInstAlias<"sra $rd, $shamt",
H A DMipsMSAInstrInfo.td2602 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2603 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2604 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2605 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2607 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2609 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2611 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2613 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
3871 defm : MSAShiftPats<sra, "SRA">;
/freebsd/crypto/openssl/crypto/
H A Dsparccpuid.S209 sra %i2,%g0,%i0
222 sra %o0,%g0,%o0 ! we return signed int, remember?
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td684 def SRA : ALU_rr<0b0100000, 0b101, "sra">,
1033 def : InstAlias<"sra $rd, $rs1, $shamt",
1268 def : PatGprUimmLog2XLen<sra, SRAI>;
1313 def : PatGprGpr<shiftop<sra>, SRA>;
1867 def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
1869 def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
1884 // occurs because SimplifyDemandedBits prefers srl over sra.
2004 def : PatGprGpr<shiftopw<sra>, SRAW, i32, i64>;
2017 def : PatGprImm<sra, SRAIW, uimm5, i32>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td113 "sra\t$r, $t", []> {
152 [(set AR:$r, (sra AR:$t, uimm5:$sa))]> {
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td1101 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
1103 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
1105 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
1151 def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot v4i32:$vB)),
1153 def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot v4i32:$vB)))),
1155 def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot v4i32:$vB)))),
1257 def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)),
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstr64Bit.td35 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
47 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;
H A DSparcInstrAliases.td650 // signx rd -> sra rd, %g0, rd
653 // signx reg, rd -> sra reg, %g0, rd
/freebsd/usr.bin/ee/nls/hu_HU.ISO8859-2/
H A Dee.msg171 162 ".init.ee nem nyithat� meg �r�sra, konfigur�ci� nem lett mentve!"
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td402 (i32 (sra node:$a, (i32 16)))>;
407 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>;
409 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>;
411 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>;
771 [shl, srl, sra, rotr]> {
782 [shl, srl, sra, rotr]> {
793 [shl,srl,sra,rotr]> {
804 [shl,srl,sra,rotr]> {
4158 def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
4162 def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td307 [(sra node:$src0, node:$src1), (sra node:$src0, (csh_mask node:$src1))]>;
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td77 def : GINodeEquiv<G_ASHR, sra>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td372 def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
1183 def: Pat<(sra I32:$Rs, (i32 16)), (A2_asrh I32:$Rs)>;
1290 def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)),
1292 def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)),
1451 def: Pat<(sra V2I32:$b, (v2i32 (splat_vector u5_0ImmPred:$c))),
1457 def: Pat<(sra V4I16:$b, (v4i16 (splat_vector u4_0ImmPred:$c))),
1733 def: Pat<(i32 (trunc (sra (Su<Mul> Sext64:$Rs, Sext64:$Rt), (i32 32)))),
1761 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
1769 def: Pat<(sra (add (shl I32:$Rt, (i32 16)), I32:$Rs), (i32 16)),
H A DHexagonPatternsHVX.td640 def: Pat<(sra HVI8:$Vs, HVI8:$Vt),
649 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
650 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td83 def ASR16 : R16_XZ_BINOP<0b1100, 0b10, "asr16", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
114 def ASRI16 : I16_XZ_IMM5<2, "asri16", sra>;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td1521 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>;
1522 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>;
2290 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2299 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)),
2318 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)),
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td456 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
1280 def : Pat<(sra GRRegs:$src, 31),
1299 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),

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