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Searched refs:opName (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP2Instructions.td62 class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
141 multiclass VOP2Inst_e32<string opName,
144 string revOp = opName,
147 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
148 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
152 VOP2Inst_e32_VOPD<string opName, VOPProfile P, bits<5> VOPDOp,
154 string revOp = opName, bit GFX9Renamed = 0> {
155 defm NAME : VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
158 multiclass VOP2Inst_e64<string opName,
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H A DVOPInstructions.td33 class VOP <string opName> {
34 string OpName = opName;
58 class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins,
61 VOP <opName>,
62 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
67 string Mnemonic = opName;
102 class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
104 VOP_Pseudo <opName, "_e64", P, P.Outs64,
157 class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
158 VOP3_Pseudo<opName, P, pattern, 1> {
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H A DVOPCInstructions.td131 class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
134 VOP <opName>,
135 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
141 string Mnemonic = opName;
277 multiclass VOPC_Pseudos <string opName,
280 string revOp = opName,
283 def _e32 : VOPC_Pseudo <opName, P>,
284 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>,
285 VCMPXNoSDstTable<1, opName#"_e32">,
286 VCMPVCMPXTable<opName#"_e32"> {
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H A DDSInstructions.td9 class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 SIMCInstr <opName, SIEncodingFamily.NONE> {
29 string Mnemonic = opName;
53 class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
54 InstSI <ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands>,
99 class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
100 : DS_Pseudo<opName,
110 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
111 : DS_Pseudo<opName,
121 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
[all …]
H A DVOP1Instructions.td42 class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1Only = 0> :
43 VOP_Pseudo <opName, !if(VOP1Only, "", "_e32"), P, P.Outs32, P.Ins32, "", pattern> {
120 multiclass VOP1Inst <string opName, VOPProfile P,
123 defvar should_mov_imm = !or(!eq(opName, "v_mov_b32"),
124 !eq(opName, "v_mov_b64"));
128 def _e32 : VOP1_Pseudo <opName, P>;
131 def _e32 : VOP1_Pseudo <opName, P>, VOPD_Component<VOPDOp, opName>;
132 def _e64 : VOP3InstBase <opName, P, node>;
136 def _sdwa : VOP1_SDWA_Pseudo <opName, P>;
139 def _dpp : VOP1_DPP_Pseudo <opName, P>;
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H A DSMInstructions.td26 class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
41 string Mnemonic = opName;
53 class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
54 : InstSI<ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands> {
107 class SM_Probe_Pseudo <string opName, RegisterClass baseClass, OffsetMode offsets>
108 : SM_Pseudo<opName, (outs),
121 class SM_Load_Pseudo <string opName, RegisterClass baseClass,
123 : SM_Pseudo<opName, (outs dstClass:$sdst),
136 class SM_Store_Pseudo <string opName, RegisterClass baseClass,
138 : SM_Pseudo<opName, (outs), !con((ins srcClass:$sdata, baseClass:$sbase),
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H A DFLATInstructions.td21 class FLAT_Pseudo<string opName, dag outs, dag ins,
35 string Mnemonic = opName;
82 class FLAT_Real <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
83 InstSI <ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands, []>,
149 class VFLAT_Real <bits<8> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
150 InstSI <ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands, []>,
201 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
205 opName,
226 class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
228 opName,
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H A DSOPInstructions.td11 class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,
14 SIMCInstr<opName, SIEncodingFamily.NONE> {
20 string Mnemonic = opName;
30 class SOP1_Pseudo <string opName, dag outs, dag ins,
32 SOP_Pseudo<opName, outs, ins, " " # asmOps, pattern> {
81 class SOP1_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <
82 opName, (outs SReg_32:$sdst),
90 class SOP1_32R <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
91 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
95 class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo <
[all …]
H A DBUFInstructions.td50 class BUF_Pseudo <string opName, dag outs, dag ins,
53 SIMCInstr<opName, SIEncodingFamily.NONE> {
60 string Mnemonic = opName;
109 class MTBUF_Pseudo <string opName, dag outs, dag ins,
111 BUF_Pseudo <opName, outs, ins, asmOps, pattern> {
216 class MTBUF_Load_Pseudo <string opName,
224 : MTBUF_Pseudo<opName,
230 let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
236 multiclass MTBUF_Pseudo_Loads_Helper<string opName, RegisterClass vdataClass,
239 …def _OFFSET : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffs…
[all …]
H A DLDSDIRInstructions.td
H A DDSDIRInstructions.td68 class DSDIR_Common<string opName, string asm = "", dag ins, bit direct> :
78 string Mnemonic = opName;
89 class DSDIR_Pseudo<string opName, dag ins, bit direct> :
90 DSDIR_Common<opName, "", ins, direct>,
91 SIMCInstr<opName, SIEncodingFamily.NONE> {
H A DVOP3Instructions.td1090 multiclass VOP3_Real_with_name_gfx11_gfx12<bits<10> op, string opName,
1092 VOP3_Real_with_name<GFX11Gen, op, opName, asmName>,
1093 VOP3_Real_with_name<GFX12Gen, op, opName, asmName>;
1101 multiclass VOP3_Realtriple_with_name_gfx11_gfx12<bits<10> op, string opName,
1103 VOP3_Realtriple_with_name<GFX11Gen, op, opName, asmName>,
1104 VOP3_Realtriple_with_name<GFX12Gen, op, opName, asmName>;
1109 multiclass VOP3be_Real_gfx11_gfx12<bits<10> op, string opName, string asmName> :
1110 VOP3be_Real<GFX11Gen, op, opName, asmName>,
1111 VOP3be_Real<GFX12Gen, op, opName, asmName>;
1248 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName,
[all …]
H A DR600Instructions.td101 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
108 !strconcat(" ", opName,
133 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
135 R600_1OP <inst, opName,
142 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
151 !strconcat(" ", opName,
171 class R600_2OP_Helper <bits<11> inst, string opName,
174 R600_2OP <inst, opName,
183 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
192 !strconcat(" ", opName, "
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H A DSIInstrInfo.td2657 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2659 SIMCInstr<opName, SIEncodingFamily.NONE> {
2665 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
2669 SIMCInstr<opName, encodingFamily> {
2672 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
2676 SIMCInstr<opName, SIEncodingFamily.VI> {
H A DVOP3PInstructions.td1355 string opName = ps.OpName>
1356 : VOP3P_DPP<op, opName, ps.Pfl, 1>, SIMCInstr<ps.PseudoInstr, subtarget> {
1367 class VOP3P_DPP8_Base<bits<7> op, VOP_Pseudo ps, string opName = ps.OpName>
1368 : VOP3P_DPP8<op, opName, ps.Pfl> {
/freebsd/usr.bin/dtc/
H A Dinput_buffer.cc597 const char *opName; member
599 binary_operator_base(l), opName(o) {} in binary_operator()
603 std::cerr << opName; in dump_impl()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DCombine.td127 class GITypeOf<string opName> : GISpecialType {
128 string OpName = opName;