Searched refs:getTRI (Results 1 – 10 of 10) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RDFRegisters.cpp | 190 MCRegUnitMaskIterator AI(A.Reg, &getTRI()); in equal_to()
191 MCRegUnitMaskIterator BI(B.Reg, &getTRI()); in equal_to()
228 llvm::MCRegUnitMaskIterator AI(A.Reg, &getTRI()); in equal_to()
229 llvm::MCRegUnitMaskIterator BI(B.Reg, &getTRI());
283 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { in print()
298 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { in print()
313 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { in hasCoverOf()
386 for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) { in makeRegRef()
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| H A D | RDFLiveness.cpp | 64 OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{'; in operator <<()
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| H A D | RDFGraph.cpp | 873 for (unsigned R = 1, E = getPRI().getTRI().getNumRegs(); R != E; ++R) in build()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | RDFCopy.cpp | 50 const TargetRegisterInfo &TRI = DFG.getTRI(); in interpretAsCopy()
160 const TargetRegisterInfo &TRI = DFG.getTRI(); in run()
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| H A D | RDFDeadCode.cpp | 72 for (unsigned R = 0, RN = DFG.getTRI().getNumRegs(); R != RN; ++R) { in isLiveInstr()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RDFRegisters.h | 173 const TargetRegisterInfo &getTRI() const { return TRI; } in getTRI() function
206 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} in RegisterAggr()
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| H A D | RDFLiveness.h | 63 : DFG(g), TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()),
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| H A D | RDFGraph.h | 696 const TargetRegisterInfo &getTRI() const { return TRI; } in getTRI() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.h | 453 const TargetRegisterInfo *getTRI() { return TRI; } in getTRI() function
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| H A D | SIMachineScheduler.cpp | 585 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; in printDebug()
589 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; in printDebug()
1585 << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; in pickBlock()
1696 DiffSetPressure.assign(DAG->getTRI()->getNumRegPressureSets(), 0); in checkRegUsageImpact()
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