1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This header is BSD licensed so anyone can use the definitions 11 * to implement compatible drivers/servers: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of IBM nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef VIRTIO_GPU_HW_H 39 #define VIRTIO_GPU_HW_H 40 41 /* 42 * VIRTIO_GPU_CMD_CTX_* 43 * VIRTIO_GPU_CMD_*_3D 44 */ 45 #define VIRTIO_GPU_F_VIRGL 0 46 47 /* 48 * VIRTIO_GPU_CMD_GET_EDID 49 */ 50 #define VIRTIO_GPU_F_EDID 1 51 /* 52 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID 53 */ 54 #define VIRTIO_GPU_F_RESOURCE_UUID 2 55 56 /* 57 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB 58 */ 59 #define VIRTIO_GPU_F_RESOURCE_BLOB 3 60 /* 61 * VIRTIO_GPU_CMD_CREATE_CONTEXT with 62 * context_init and multiple timelines 63 */ 64 #define VIRTIO_GPU_F_CONTEXT_INIT 4 65 66 enum virtio_gpu_ctrl_type { 67 VIRTIO_GPU_UNDEFINED = 0, 68 69 /* 2d commands */ 70 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 71 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 72 VIRTIO_GPU_CMD_RESOURCE_UNREF, 73 VIRTIO_GPU_CMD_SET_SCANOUT, 74 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 75 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 76 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 77 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 78 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 79 VIRTIO_GPU_CMD_GET_CAPSET, 80 VIRTIO_GPU_CMD_GET_EDID, 81 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 82 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB, 83 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB, 84 85 /* 3d commands */ 86 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 87 VIRTIO_GPU_CMD_CTX_DESTROY, 88 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 89 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 90 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 91 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 92 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 93 VIRTIO_GPU_CMD_SUBMIT_3D, 94 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB, 95 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB, 96 97 /* cursor commands */ 98 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 99 VIRTIO_GPU_CMD_MOVE_CURSOR, 100 101 /* success responses */ 102 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 103 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 104 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 105 VIRTIO_GPU_RESP_OK_CAPSET, 106 VIRTIO_GPU_RESP_OK_EDID, 107 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 108 VIRTIO_GPU_RESP_OK_MAP_INFO, 109 110 /* error responses */ 111 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 112 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 113 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 114 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 115 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 116 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 117 }; 118 119 enum virtio_gpu_shm_id { 120 VIRTIO_GPU_SHM_ID_UNDEFINED = 0, 121 /* 122 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB 123 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB 124 */ 125 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 126 }; 127 128 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 129 /* 130 * If the following flag is set, then ring_idx contains the index 131 * of the command ring that needs to used when creating the fence 132 */ 133 #define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1) 134 135 struct virtio_gpu_ctrl_hdr { 136 uint32_t type; 137 uint32_t flags; 138 uint64_t fence_id; 139 uint32_t ctx_id; 140 uint8_t ring_idx; 141 uint8_t padding[3]; 142 }; 143 144 /* data passed in the cursor vq */ 145 146 struct virtio_gpu_cursor_pos { 147 uint32_t scanout_id; 148 uint32_t x; 149 uint32_t y; 150 uint32_t padding; 151 }; 152 153 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ 154 struct virtio_gpu_update_cursor { 155 struct virtio_gpu_ctrl_hdr hdr; 156 struct virtio_gpu_cursor_pos pos; /* update & move */ 157 uint32_t resource_id; /* update only */ 158 uint32_t hot_x; /* update only */ 159 uint32_t hot_y; /* update only */ 160 uint32_t padding; 161 }; 162 163 /* data passed in the control vq, 2d related */ 164 165 struct virtio_gpu_rect { 166 uint32_t x; 167 uint32_t y; 168 uint32_t width; 169 uint32_t height; 170 }; 171 172 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */ 173 struct virtio_gpu_resource_unref { 174 struct virtio_gpu_ctrl_hdr hdr; 175 uint32_t resource_id; 176 uint32_t padding; 177 }; 178 179 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ 180 struct virtio_gpu_resource_create_2d { 181 struct virtio_gpu_ctrl_hdr hdr; 182 uint32_t resource_id; 183 uint32_t format; 184 uint32_t width; 185 uint32_t height; 186 }; 187 188 /* VIRTIO_GPU_CMD_SET_SCANOUT */ 189 struct virtio_gpu_set_scanout { 190 struct virtio_gpu_ctrl_hdr hdr; 191 struct virtio_gpu_rect r; 192 uint32_t scanout_id; 193 uint32_t resource_id; 194 }; 195 196 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ 197 struct virtio_gpu_resource_flush { 198 struct virtio_gpu_ctrl_hdr hdr; 199 struct virtio_gpu_rect r; 200 uint32_t resource_id; 201 uint32_t padding; 202 }; 203 204 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ 205 struct virtio_gpu_transfer_to_host_2d { 206 struct virtio_gpu_ctrl_hdr hdr; 207 struct virtio_gpu_rect r; 208 uint64_t offset; 209 uint32_t resource_id; 210 uint32_t padding; 211 }; 212 213 struct virtio_gpu_mem_entry { 214 uint64_t addr; 215 uint32_t length; 216 uint32_t padding; 217 }; 218 219 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ 220 struct virtio_gpu_resource_attach_backing { 221 struct virtio_gpu_ctrl_hdr hdr; 222 uint32_t resource_id; 223 uint32_t nr_entries; 224 }; 225 226 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ 227 struct virtio_gpu_resource_detach_backing { 228 struct virtio_gpu_ctrl_hdr hdr; 229 uint32_t resource_id; 230 uint32_t padding; 231 }; 232 233 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ 234 #define VIRTIO_GPU_MAX_SCANOUTS 16 235 struct virtio_gpu_resp_display_info { 236 struct virtio_gpu_ctrl_hdr hdr; 237 struct virtio_gpu_display_one { 238 struct virtio_gpu_rect r; 239 uint32_t enabled; 240 uint32_t flags; 241 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 242 }; 243 244 /* data passed in the control vq, 3d related */ 245 246 struct virtio_gpu_box { 247 uint32_t x, y, z; 248 uint32_t w, h, d; 249 }; 250 251 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */ 252 struct virtio_gpu_transfer_host_3d { 253 struct virtio_gpu_ctrl_hdr hdr; 254 struct virtio_gpu_box box; 255 uint64_t offset; 256 uint32_t resource_id; 257 uint32_t level; 258 uint32_t stride; 259 uint32_t layer_stride; 260 }; 261 262 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ 263 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 264 struct virtio_gpu_resource_create_3d { 265 struct virtio_gpu_ctrl_hdr hdr; 266 uint32_t resource_id; 267 uint32_t target; 268 uint32_t format; 269 uint32_t bind; 270 uint32_t width; 271 uint32_t height; 272 uint32_t depth; 273 uint32_t array_size; 274 uint32_t last_level; 275 uint32_t nr_samples; 276 uint32_t flags; 277 uint32_t padding; 278 }; 279 280 /* VIRTIO_GPU_CMD_CTX_CREATE */ 281 #define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff 282 struct virtio_gpu_ctx_create { 283 struct virtio_gpu_ctrl_hdr hdr; 284 uint32_t nlen; 285 uint32_t context_init; 286 char debug_name[64]; 287 }; 288 289 /* VIRTIO_GPU_CMD_CTX_DESTROY */ 290 struct virtio_gpu_ctx_destroy { 291 struct virtio_gpu_ctrl_hdr hdr; 292 }; 293 294 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */ 295 struct virtio_gpu_ctx_resource { 296 struct virtio_gpu_ctrl_hdr hdr; 297 uint32_t resource_id; 298 uint32_t padding; 299 }; 300 301 /* VIRTIO_GPU_CMD_SUBMIT_3D */ 302 struct virtio_gpu_cmd_submit { 303 struct virtio_gpu_ctrl_hdr hdr; 304 uint32_t size; 305 uint32_t padding; 306 }; 307 308 #define VIRTIO_GPU_CAPSET_VIRGL 1 309 #define VIRTIO_GPU_CAPSET_VIRGL2 2 310 311 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ 312 struct virtio_gpu_get_capset_info { 313 struct virtio_gpu_ctrl_hdr hdr; 314 uint32_t capset_index; 315 uint32_t padding; 316 }; 317 318 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ 319 struct virtio_gpu_resp_capset_info { 320 struct virtio_gpu_ctrl_hdr hdr; 321 uint32_t capset_id; 322 uint32_t capset_max_version; 323 uint32_t capset_max_size; 324 uint32_t padding; 325 }; 326 327 /* VIRTIO_GPU_CMD_GET_CAPSET */ 328 struct virtio_gpu_get_capset { 329 struct virtio_gpu_ctrl_hdr hdr; 330 uint32_t capset_id; 331 uint32_t capset_version; 332 }; 333 334 /* VIRTIO_GPU_RESP_OK_CAPSET */ 335 struct virtio_gpu_resp_capset { 336 struct virtio_gpu_ctrl_hdr hdr; 337 uint8_t capset_data[]; 338 }; 339 340 /* VIRTIO_GPU_CMD_GET_EDID */ 341 struct virtio_gpu_cmd_get_edid { 342 struct virtio_gpu_ctrl_hdr hdr; 343 uint32_t scanout; 344 uint32_t padding; 345 }; 346 347 /* VIRTIO_GPU_RESP_OK_EDID */ 348 struct virtio_gpu_resp_edid { 349 struct virtio_gpu_ctrl_hdr hdr; 350 uint32_t size; 351 uint32_t padding; 352 uint8_t edid[1024]; 353 }; 354 355 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 356 357 struct virtio_gpu_config { 358 uint32_t events_read; 359 uint32_t events_clear; 360 uint32_t num_scanouts; 361 uint32_t num_capsets; 362 }; 363 364 /* simple formats for fbcon/X use */ 365 enum virtio_gpu_formats { 366 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 367 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 368 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 369 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 370 371 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 372 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 373 374 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 375 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 376 }; 377 378 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */ 379 struct virtio_gpu_resource_assign_uuid { 380 struct virtio_gpu_ctrl_hdr hdr; 381 uint32_t resource_id; 382 uint32_t padding; 383 }; 384 385 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */ 386 struct virtio_gpu_resp_resource_uuid { 387 struct virtio_gpu_ctrl_hdr hdr; 388 uint8_t uuid[16]; 389 }; 390 391 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */ 392 struct virtio_gpu_resource_create_blob { 393 struct virtio_gpu_ctrl_hdr hdr; 394 uint32_t resource_id; 395 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001 396 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002 397 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003 398 399 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001 400 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002 401 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 402 /* zero is invalid blob mem */ 403 uint32_t blob_mem; 404 uint32_t blob_flags; 405 uint32_t nr_entries; 406 uint64_t blob_id; 407 uint64_t size; 408 /* 409 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow 410 */ 411 }; 412 413 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */ 414 struct virtio_gpu_set_scanout_blob { 415 struct virtio_gpu_ctrl_hdr hdr; 416 struct virtio_gpu_rect r; 417 uint32_t scanout_id; 418 uint32_t resource_id; 419 uint32_t width; 420 uint32_t height; 421 uint32_t format; 422 uint32_t padding; 423 uint32_t strides[4]; 424 uint32_t offsets[4]; 425 }; 426 427 /* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */ 428 struct virtio_gpu_resource_map_blob { 429 struct virtio_gpu_ctrl_hdr hdr; 430 uint32_t resource_id; 431 uint32_t padding; 432 uint64_t offset; 433 }; 434 435 /* VIRTIO_GPU_RESP_OK_MAP_INFO */ 436 #define VIRTIO_GPU_MAP_CACHE_MASK 0x0f 437 #define VIRTIO_GPU_MAP_CACHE_NONE 0x00 438 #define VIRTIO_GPU_MAP_CACHE_CACHED 0x01 439 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02 440 #define VIRTIO_GPU_MAP_CACHE_WC 0x03 441 struct virtio_gpu_resp_map_info { 442 struct virtio_gpu_ctrl_hdr hdr; 443 uint32_t map_info; 444 uint32_t padding; 445 }; 446 447 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */ 448 struct virtio_gpu_resource_unmap_blob { 449 struct virtio_gpu_ctrl_hdr hdr; 450 uint32_t resource_id; 451 uint32_t padding; 452 }; 453 454 #endif 455