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Searched refs:UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV (Results 1 – 1 of 1) sorted by relevance

/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c213 #define UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20) macro
605 reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0); in uphy_pex_enable()
606 reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19); in uphy_pex_enable()