| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | nau8824.txt | 30 …eshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated…
31 SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
47 - nuvoton,sar-compare-time: SAR compare time
53 - nuvoton,sar-sampling-time: SAR sampling time
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| H A D | nau8825.txt | 34 …eshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated…
35 SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
51 - nuvoton,sar-compare-time: SAR compare time
57 - nuvoton,sar-sampling-time: SAR sampling time
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaRegisterInfo.td | 76 def SAR : SRReg<3, "sar", ["SAR","3"]>;
78 def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR)>;
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| H A D | XtensaInstrInfo.td | 106 let Uses = [SAR] in {
126 let Defs = [SAR] in {
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | amlogic,meson-saradc.txt | 1 * Amlogic Meson SAR (Successive Approximation Register) A/D converter
19 - "core" for the SAR ADC core clock
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| /freebsd/share/monetdef_unicode/ |
| H A D | ar_SA.UTF-8.src | 7 SAR
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| /freebsd/sys/dev/xdma/controller/ |
| H A D | pl330.h | 47 #define SAR(n) (0x400 + 0x20 * (n)) /* Source address for DMA channel n */ macro
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| H A D | pl330.c | 168 READ4(sc, SAR(0)), READ4(sc, DAR(0))); in pl330_intr()
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mvebu-core-clock.txt | 4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
67 - reg : shall be the register address of the Sample-At-Reset (SAR) register
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCopyPhysRegs.cpp | 94 BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp); in visitMBB()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VERegisterInfo.td | 65 def SAR : VEMiscReg<2, "sar">; // Store address register
78 (add USRCC, PSW, SAR, PMMR,
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | rohm,bd70528-pmic.txt | 8 dual-input power path, 10 bit SAR ADC for battery temperature monitor and
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/ |
| H A D | XtensaDisassembler.cpp | 78 static const unsigned SRDecoderTable[] = {Xtensa::SAR, 3};
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-synology-ds414.dts | 72 * pin being sampled at reset (bit 0 of SAR).
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| H A D | armada-385-clearfog-gtr.dtsi | 50 47 - Control isolation of boot sensitive SAR signals
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 6530 bool SCEVToValueExpr(const llvm::SCEVAddRecExpr &SAR, ScalarEvolution &SE) { in SCEVToValueExpr()
6531 assert(SAR.isAffine() && "Expected affine SCEV"); in SCEVToValueExpr()
6533 if (isa<SCEVAddRecExpr>(SAR.getStart())) in SCEVToValueExpr()
6536 const SCEV *Start = SAR.getStart(); in SCEVToValueExpr()
6537 const SCEV *Stride = SAR.getStepRecurrence(SE); in SCEVToValueExpr()
6600 bool SCEVToIterCountExpr(const llvm::SCEVAddRecExpr &SAR, in SCEVToIterCountExpr()
6602 assert(SAR.isAffine() && "Expected affine SCEV"); in SCEVToIterCountExpr()
6603 if (isa<SCEVAddRecExpr>(SAR.getStart())) { in SCEVToIterCountExpr()
6605 << SAR << '\n'); in SCEVToIterCountExpr()
6608 const SCEV *Start = SAR.getStart(); in SCEVToIterCountExpr()
[all …]
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| /freebsd/usr.bin/units/ |
| H A D | definitions.units | 486 SAR saudiarabiariyal
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SchedSandyBridge.td | 952 def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1032 "SAR(8|16|32|64)mCL",
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| H A D | X86SchedBroadwell.td | 1013 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1166 "SAR(8|16|32|64)mCL",
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| H A D | X86SchedSkylakeClient.td | 1044 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1231 "SAR(8|16|32|64)mCL",
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| H A D | X86SchedHaswell.td | 1092 def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
1325 "SAR(8|16|32|64)mCL",
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| H A D | X86ScheduleAtom.td | 514 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
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| H A D | X86SchedSkylakeServer.td | 1234 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1618 "SAR(8|16|32|64)mCL",
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 135 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
|