Searched refs:R9A07G043_CLK_P0_DIV2 (Results 1 – 2 of 2) sorted by relevance
29 #define R9A07G043_CLK_P0_DIV2 18 macro
420 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,423 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;