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Searched refs:LC0 (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/dev/xdma/controller/
H A Dpl330.h62 #define LC0(n) (0x40C + 0x20 * (n)) /* Loop counter 0 for DMA channel n */ macro
H A Dpl330.c167 __func__, pending, READ4(sc, LC0(0)), in pl330_intr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.h111 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R || in isLoopRegister()
H A DHexagonMCChecker.cpp47 Defs[Hexagon::LC0].insert(Unconditional); in init()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
H A DHexagonRegisterInfo.cpp163 Reserved.set(Hexagon::LC0); // C1 in getReservedRegs()
H A DHexagonRegisterInfo.td174 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>;
206 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
560 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
H A DHexagonHardwareLoops.cpp1007 static const Register Regs01[] = { LC0, SA0, LC1, SA1 }; in isInvalidLoopOperation()
H A DHexagonISelLowering.cpp328 .Case("lc0", Hexagon::LC0) in getRegisterByName()
H A DHexagonDepInstrInfo.td5022 let Uses = [LC0, SA0];
5023 let Defs = [LC0, P3, PC, USR];
5033 let Uses = [LC0, LC1, SA0, SA1];
5034 let Defs = [LC0, LC1, P3, PC, USR];
5646 let Defs = [LC0, SA0, USR];
5664 let Defs = [LC0, SA0, USR];
5728 let Defs = [LC0, P3, SA0, USR];
5747 let Defs = [LC0, P3, SA0, USR];
5765 let Defs = [LC0, P3, SA0, USR];
5784 let Defs = [LC0, P
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp675 /* 0 */ SA0, LC0, SA1, LC1, in DecodeCtrRegsRegisterClass()