1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/lock.h>
33 #include <sys/module.h>
34 #include <sys/mutex.h>
35 #include <sys/rman.h>
36 #include <sys/resource.h>
37 #include <machine/bus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41
42 #include <dev/clk/clk.h>
43 #include <dev/hwreset/hwreset.h>
44 #include <dev/syscon/syscon.h>
45
46 #include "syscon_if.h"
47
48 #include "opt_snd.h"
49 #include <dev/sound/pcm/sound.h>
50 #include <dev/sound/fdt/audio_dai.h>
51 #include "audio_dai_if.h"
52
53 #define I2S_TXCR 0x0000
54 #define I2S_CSR_2 (0 << 15)
55 #define I2S_CSR_4 (1 << 15)
56 #define I2S_CSR_6 (2 << 15)
57 #define I2S_CSR_8 (3 << 15)
58 #define I2S_TXCR_IBM_NORMAL (0 << 9)
59 #define I2S_TXCR_IBM_LJ (1 << 9)
60 #define I2S_TXCR_IBM_RJ (2 << 9)
61 #define I2S_TXCR_PBM_NODELAY (0 << 7)
62 #define I2S_TXCR_PBM_1 (1 << 7)
63 #define I2S_TXCR_PBM_2 (2 << 7)
64 #define I2S_TXCR_PBM_3 (3 << 7)
65 #define I2S_TXCR_TFS_I2S (0 << 5)
66 #define I2S_TXCR_TFS_PCM (1 << 5)
67 #define I2S_TXCR_VDW_16 (0xf << 0)
68 #define I2S_RXCR 0x0004
69 #define I2S_RXCR_IBM_NORMAL (0 << 9)
70 #define I2S_RXCR_IBM_LJ (1 << 9)
71 #define I2S_RXCR_IBM_RJ (2 << 9)
72 #define I2S_RXCR_PBM_NODELAY (0 << 7)
73 #define I2S_RXCR_PBM_1 (1 << 7)
74 #define I2S_RXCR_PBM_2 (2 << 7)
75 #define I2S_RXCR_PBM_3 (3 << 7)
76 #define I2S_RXCR_TFS_I2S (0 << 5)
77 #define I2S_RXCR_TFS_PCM (1 << 5)
78 #define I2S_RXCR_VDW_16 (0xf << 0)
79 #define I2S_CKR 0x0008
80 #define I2S_CKR_MSS_MASK (1 << 27)
81 #define I2S_CKR_MSS_MASTER (0 << 27)
82 #define I2S_CKR_MSS_SLAVE (1 << 27)
83 #define I2S_CKR_CKP (1 << 26)
84 #define I2S_CKR_MDIV(n) (((n) - 1) << 16)
85 #define I2S_CKR_MDIV_MASK (0xff << 16)
86 #define I2S_CKR_RSD(n) (((n) - 1) << 8)
87 #define I2S_CKR_RSD_MASK (0xff << 8)
88 #define I2S_CKR_TSD(n) (((n) - 1) << 0)
89 #define I2S_CKR_TSD_MASK (0xff << 0)
90 #define I2S_TXFIFOLR 0x000c
91 #define TXFIFO0LR_MASK 0x3f
92 #define I2S_DMACR 0x0010
93 #define I2S_DMACR_RDE_ENABLE (1 << 24)
94 #define I2S_DMACR_RDL(n) ((n) << 16)
95 #define I2S_DMACR_TDE_ENABLE (1 << 8)
96 #define I2S_DMACR_TDL(n) ((n) << 0)
97 #define I2S_INTCR 0x0014
98 #define I2S_INTCR_RFT(n) (((n) - 1) << 20)
99 #define I2S_INTCR_TFT(n) (((n) - 1) << 4)
100 #define I2S_INTCR_RXFIE (1 << 16)
101 #define I2S_INTCR_TXUIC (1 << 2)
102 #define I2S_INTCR_TXEIE (1 << 0)
103 #define I2S_INTSR 0x0018
104 #define I2S_INTSR_RXFI (1 << 16)
105 #define I2S_INTSR_TXUI (1 << 1)
106 #define I2S_INTSR_TXEI (1 << 0)
107 #define I2S_XFER 0x001c
108 #define I2S_XFER_RXS_START (1 << 1)
109 #define I2S_XFER_TXS_START (1 << 0)
110 #define I2S_CLR 0x0020
111 #define I2S_CLR_RXC (1 << 1)
112 #define I2S_CLR_TXC (1 << 0)
113 #define I2S_TXDR 0x0024
114 #define I2S_RXDR 0x0028
115 #define I2S_RXFIFOLR 0x002c
116 #define RXFIFO0LR_MASK 0x3f
117
118 /* syscon */
119 #define GRF_SOC_CON8 0xe220
120 #define I2S_IO_DIRECTION_MASK 7
121 #define I2S_IO_DIRECTION_SHIFT 11
122 #define I2S_IO_8CH_OUT_2CH_IN 0
123 #define I2S_IO_6CH_OUT_4CH_IN 4
124 #define I2S_IO_4CH_OUT_6CH_IN 6
125 #define I2S_IO_2CH_OUT_8CH_IN 7
126
127 #define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d))
128
129 #define RK_I2S_SAMPLING_RATE 48000
130 #define FIFO_SIZE 32
131
132 static struct ofw_compat_data compat_data[] = {
133 { "rockchip,rk3066-i2s", 1 },
134 { "rockchip,rk3399-i2s", 1 },
135 { NULL, 0 }
136 };
137
138 static struct resource_spec rk_i2s_spec[] = {
139 { SYS_RES_MEMORY, 0, RF_ACTIVE },
140 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
141 { -1, 0 }
142 };
143
144 struct rk_i2s_softc {
145 device_t dev;
146 struct resource *res[2];
147 struct mtx mtx;
148 clk_t clk;
149 clk_t hclk;
150 void * intrhand;
151 struct syscon *grf;
152 /* pointers to playback/capture buffers */
153 uint32_t play_ptr;
154 uint32_t rec_ptr;
155 };
156
157 #define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx)
158 #define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
159 #define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
160 #define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
161
162 static int rk_i2s_probe(device_t dev);
163 static int rk_i2s_attach(device_t dev);
164 static int rk_i2s_detach(device_t dev);
165
166 static uint32_t sc_fmt[] = {
167 SND_FORMAT(AFMT_S16_LE, 2, 0),
168 0
169 };
170 static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0};
171
172
173 static int
rk_i2s_init(struct rk_i2s_softc * sc)174 rk_i2s_init(struct rk_i2s_softc *sc)
175 {
176 uint32_t val;
177 int error;
178
179 clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256,
180 CLK_SET_ROUND_DOWN);
181 error = clk_enable(sc->clk);
182 if (error != 0) {
183 device_printf(sc->dev, "cannot enable i2s_clk clock\n");
184 return (ENXIO);
185 }
186
187 val = I2S_INTCR_TFT(FIFO_SIZE/2);
188 val |= I2S_INTCR_RFT(FIFO_SIZE/2);
189 RK_I2S_WRITE_4(sc, I2S_INTCR, val);
190
191 if (sc->grf && ofw_bus_is_compatible(sc->dev, "rockchip,rk3399-i2s")) {
192 val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT);
193 val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16;
194 SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val);
195
196 #if 0
197 // HACK: enable IO domain
198 val = (1 << 1);
199 val |= (1 << 1) << 16;
200 SYSCON_WRITE_4(sc->grf, 0xe640, val);
201 #endif
202 }
203
204 RK_I2S_WRITE_4(sc, I2S_XFER, 0);
205
206 return (0);
207 }
208
209 static int
rk_i2s_probe(device_t dev)210 rk_i2s_probe(device_t dev)
211 {
212 if (!ofw_bus_status_okay(dev))
213 return (ENXIO);
214
215 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
216 return (ENXIO);
217
218 device_set_desc(dev, "Rockchip I2S");
219 return (BUS_PROBE_DEFAULT);
220 }
221
222 static int
rk_i2s_attach(device_t dev)223 rk_i2s_attach(device_t dev)
224 {
225 struct rk_i2s_softc *sc;
226 int error;
227 phandle_t node;
228
229 sc = device_get_softc(dev);
230 sc->dev = dev;
231
232 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
233
234 if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) {
235 device_printf(dev, "cannot allocate resources for device\n");
236 error = ENXIO;
237 goto fail;
238 }
239
240 error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk);
241 if (error != 0) {
242 device_printf(dev, "cannot get i2s_hclk clock\n");
243 goto fail;
244 }
245
246 error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk);
247 if (error != 0) {
248 device_printf(dev, "cannot get i2s_clk clock\n");
249 goto fail;
250 }
251
252 /* Activate the module clock. */
253 error = clk_enable(sc->hclk);
254 if (error != 0) {
255 device_printf(dev, "cannot enable i2s_hclk clock\n");
256 goto fail;
257 }
258
259 node = ofw_bus_get_node(dev);
260 if (OF_hasprop(node, "rockchip,grf") &&
261 syscon_get_by_ofw_property(dev, node,
262 "rockchip,grf", &sc->grf) != 0) {
263 device_printf(dev, "cannot get grf driver handle\n");
264 return (ENXIO);
265 }
266
267 rk_i2s_init(sc);
268
269 OF_device_register_xref(OF_xref_from_node(node), dev);
270
271 return (0);
272
273 fail:
274 rk_i2s_detach(dev);
275 return (error);
276 }
277
278 static int
rk_i2s_detach(device_t dev)279 rk_i2s_detach(device_t dev)
280 {
281 struct rk_i2s_softc *i2s;
282
283 i2s = device_get_softc(dev);
284
285 if (i2s->hclk != NULL)
286 clk_release(i2s->hclk);
287 if (i2s->clk)
288 clk_release(i2s->clk);
289
290 if (i2s->intrhand != NULL)
291 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand);
292
293 bus_release_resources(dev, rk_i2s_spec, i2s->res);
294 mtx_destroy(&i2s->mtx);
295
296 return (0);
297 }
298
299 static int
rk_i2s_dai_init(device_t dev,uint32_t format)300 rk_i2s_dai_init(device_t dev, uint32_t format)
301 {
302 uint32_t val, txcr, rxcr;
303 struct rk_i2s_softc *sc;
304 int fmt, pol, clk;
305
306 sc = device_get_softc(dev);
307
308 fmt = AUDIO_DAI_FORMAT_FORMAT(format);
309 pol = AUDIO_DAI_FORMAT_POLARITY(format);
310 clk = AUDIO_DAI_FORMAT_CLOCK(format);
311
312 /* Set format */
313 val = RK_I2S_READ_4(sc, I2S_CKR);
314
315 val &= ~(I2S_CKR_MSS_MASK);
316 switch (clk) {
317 case AUDIO_DAI_CLOCK_CBM_CFM:
318 val |= I2S_CKR_MSS_MASTER;
319 break;
320 case AUDIO_DAI_CLOCK_CBS_CFS:
321 val |= I2S_CKR_MSS_SLAVE;
322 break;
323 default:
324 return (EINVAL);
325 }
326
327 switch (pol) {
328 case AUDIO_DAI_POLARITY_IB_NF:
329 val |= I2S_CKR_CKP;
330 break;
331 case AUDIO_DAI_POLARITY_NB_NF:
332 val &= ~I2S_CKR_CKP;
333 break;
334 default:
335 return (EINVAL);
336 }
337
338 RK_I2S_WRITE_4(sc, I2S_CKR, val);
339
340 txcr = I2S_TXCR_VDW_16 | I2S_CSR_2;
341 rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2;
342
343 switch (fmt) {
344 case AUDIO_DAI_FORMAT_I2S:
345 txcr |= I2S_TXCR_IBM_NORMAL;
346 rxcr |= I2S_RXCR_IBM_NORMAL;
347 break;
348 case AUDIO_DAI_FORMAT_LJ:
349 txcr |= I2S_TXCR_IBM_LJ;
350 rxcr |= I2S_RXCR_IBM_LJ;
351 break;
352 case AUDIO_DAI_FORMAT_RJ:
353 txcr |= I2S_TXCR_IBM_RJ;
354 rxcr |= I2S_RXCR_IBM_RJ;
355 break;
356 case AUDIO_DAI_FORMAT_DSPA:
357 txcr |= I2S_TXCR_TFS_PCM;
358 rxcr |= I2S_RXCR_TFS_PCM;
359 txcr |= I2S_TXCR_PBM_1;
360 rxcr |= I2S_RXCR_PBM_1;
361 break;
362 case AUDIO_DAI_FORMAT_DSPB:
363 txcr |= I2S_TXCR_TFS_PCM;
364 rxcr |= I2S_RXCR_TFS_PCM;
365 txcr |= I2S_TXCR_PBM_2;
366 rxcr |= I2S_RXCR_PBM_2;
367 break;
368 default:
369 return EINVAL;
370 }
371
372 RK_I2S_WRITE_4(sc, I2S_TXCR, txcr);
373 RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr);
374
375 RK_I2S_WRITE_4(sc, I2S_XFER, 0);
376
377 return (0);
378 }
379
380
381 static int
rk_i2s_dai_intr(device_t dev,struct snd_dbuf * play_buf,struct snd_dbuf * rec_buf)382 rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf)
383 {
384 struct rk_i2s_softc *sc;
385 uint32_t status;
386 uint32_t level;
387 uint32_t val = 0x00;
388 int ret = 0;
389
390 sc = device_get_softc(dev);
391
392 RK_I2S_LOCK(sc);
393 status = RK_I2S_READ_4(sc, I2S_INTSR);
394
395 if (status & I2S_INTSR_TXEI) {
396 level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK;
397 uint8_t *samples;
398 uint32_t count, size, readyptr, written;
399 count = sndbuf_getready(play_buf);
400 if (count > FIFO_SIZE - 1)
401 count = FIFO_SIZE - 1;
402 size = sndbuf_getsize(play_buf);
403 readyptr = sndbuf_getreadyptr(play_buf);
404
405 samples = (uint8_t*)sndbuf_getbuf(play_buf);
406 written = 0;
407 for (; level < count; level++) {
408 val = (samples[readyptr++ % size] << 0);
409 val |= (samples[readyptr++ % size] << 8);
410 val |= (samples[readyptr++ % size] << 16);
411 val |= (samples[readyptr++ % size] << 24);
412 written += 4;
413 RK_I2S_WRITE_4(sc, I2S_TXDR, val);
414 }
415 sc->play_ptr += written;
416 sc->play_ptr %= size;
417 ret |= AUDIO_DAI_PLAY_INTR;
418 }
419
420 if (status & I2S_INTSR_RXFI) {
421 level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK;
422 uint8_t *samples;
423 uint32_t count, size, freeptr, recorded;
424 count = sndbuf_getfree(rec_buf);
425 size = sndbuf_getsize(rec_buf);
426 freeptr = sndbuf_getfreeptr(rec_buf);
427 samples = (uint8_t*)sndbuf_getbuf(rec_buf);
428 recorded = 0;
429 if (level > count / 4)
430 level = count / 4;
431
432 for (; level > 0; level--) {
433 val = RK_I2S_READ_4(sc, I2S_RXDR);
434 samples[freeptr++ % size] = val & 0xff;
435 samples[freeptr++ % size] = (val >> 8) & 0xff;
436 samples[freeptr++ % size] = (val >> 16) & 0xff;
437 samples[freeptr++ % size] = (val >> 24) & 0xff;
438 recorded += 4;
439 }
440 sc->rec_ptr += recorded;
441 sc->rec_ptr %= size;
442 ret |= AUDIO_DAI_REC_INTR;
443 }
444
445 RK_I2S_UNLOCK(sc);
446
447 return (ret);
448 }
449
450 static struct pcmchan_caps *
rk_i2s_dai_get_caps(device_t dev)451 rk_i2s_dai_get_caps(device_t dev)
452 {
453 return (&rk_i2s_caps);
454 }
455
456 static int
rk_i2s_dai_trigger(device_t dev,int go,int pcm_dir)457 rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir)
458 {
459 struct rk_i2s_softc *sc = device_get_softc(dev);
460 uint32_t val;
461 uint32_t clear_bit;
462
463 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC))
464 return (EINVAL);
465
466 switch (go) {
467 case PCMTRIG_START:
468 val = RK_I2S_READ_4(sc, I2S_INTCR);
469 if (pcm_dir == PCMDIR_PLAY)
470 val |= I2S_INTCR_TXEIE;
471 else if (pcm_dir == PCMDIR_REC)
472 val |= I2S_INTCR_RXFIE;
473 RK_I2S_WRITE_4(sc, I2S_INTCR, val);
474
475 val = I2S_XFER_TXS_START | I2S_XFER_RXS_START;
476 RK_I2S_WRITE_4(sc, I2S_XFER, val);
477 break;
478
479 case PCMTRIG_STOP:
480 case PCMTRIG_ABORT:
481 val = RK_I2S_READ_4(sc, I2S_INTCR);
482 if (pcm_dir == PCMDIR_PLAY)
483 val &= ~I2S_INTCR_TXEIE;
484 else if (pcm_dir == PCMDIR_REC)
485 val &= ~I2S_INTCR_RXFIE;
486 RK_I2S_WRITE_4(sc, I2S_INTCR, val);
487
488 /*
489 * If there is no other activity going on, stop transfers
490 */
491 if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) {
492 RK_I2S_WRITE_4(sc, I2S_XFER, 0);
493
494 if (pcm_dir == PCMDIR_PLAY)
495 clear_bit = I2S_CLR_TXC;
496 else if (pcm_dir == PCMDIR_REC)
497 clear_bit = I2S_CLR_RXC;
498 else
499 return (EINVAL);
500
501 val = RK_I2S_READ_4(sc, I2S_CLR);
502 val |= clear_bit;
503 RK_I2S_WRITE_4(sc, I2S_CLR, val);
504
505 while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0)
506 DELAY(1);
507 }
508
509 RK_I2S_LOCK(sc);
510 if (pcm_dir == PCMDIR_PLAY)
511 sc->play_ptr = 0;
512 else
513 sc->rec_ptr = 0;
514 RK_I2S_UNLOCK(sc);
515 break;
516 }
517
518 return (0);
519 }
520
521 static uint32_t
rk_i2s_dai_get_ptr(device_t dev,int pcm_dir)522 rk_i2s_dai_get_ptr(device_t dev, int pcm_dir)
523 {
524 struct rk_i2s_softc *sc;
525 uint32_t ptr;
526
527 sc = device_get_softc(dev);
528
529 RK_I2S_LOCK(sc);
530 if (pcm_dir == PCMDIR_PLAY)
531 ptr = sc->play_ptr;
532 else
533 ptr = sc->rec_ptr;
534 RK_I2S_UNLOCK(sc);
535
536 return ptr;
537 }
538
539 static int
rk_i2s_dai_setup_intr(device_t dev,driver_intr_t intr_handler,void * intr_arg)540 rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg)
541 {
542 struct rk_i2s_softc *sc = device_get_softc(dev);
543
544 if (bus_setup_intr(dev, sc->res[1],
545 INTR_TYPE_AV | INTR_MPSAFE, NULL, intr_handler, intr_arg,
546 &sc->intrhand)) {
547 device_printf(dev, "cannot setup interrupt handler\n");
548 return (ENXIO);
549 }
550
551 return (0);
552 }
553
554 static uint32_t
rk_i2s_dai_set_chanformat(device_t dev,uint32_t format)555 rk_i2s_dai_set_chanformat(device_t dev, uint32_t format)
556 {
557
558 return (0);
559 }
560
561 static int
rk_i2s_dai_set_sysclk(device_t dev,unsigned int rate,int dai_dir)562 rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir)
563 {
564 struct rk_i2s_softc *sc;
565 int error;
566
567 sc = device_get_softc(dev);
568 error = clk_disable(sc->clk);
569 if (error != 0) {
570 device_printf(sc->dev, "could not disable i2s_clk clock\n");
571 return (error);
572 }
573
574 error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN);
575 if (error != 0)
576 device_printf(sc->dev, "could not set i2s_clk freq\n");
577
578 error = clk_enable(sc->clk);
579 if (error != 0) {
580 device_printf(sc->dev, "could not enable i2s_clk clock\n");
581 return (error);
582 }
583
584 return (0);
585 }
586
587 static uint32_t
rk_i2s_dai_set_chanspeed(device_t dev,uint32_t speed)588 rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed)
589 {
590 struct rk_i2s_softc *sc;
591 int error;
592 uint32_t val;
593 uint32_t bus_clock_div, lr_clock_div;
594 uint64_t bus_clk_freq;
595 uint64_t clk_freq;
596
597 sc = device_get_softc(dev);
598
599 /* Set format */
600 val = RK_I2S_READ_4(sc, I2S_CKR);
601
602 if ((val & I2S_CKR_MSS_SLAVE) == 0) {
603 error = clk_get_freq(sc->clk, &clk_freq);
604 if (error != 0) {
605 device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error);
606 return (error);
607 }
608 bus_clk_freq = 2 * 32 * speed;
609 bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq);
610 lr_clock_div = bus_clk_freq / speed;
611
612 val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK);
613 val |= I2S_CKR_MDIV(bus_clock_div);
614 val |= I2S_CKR_RSD(lr_clock_div);
615 val |= I2S_CKR_TSD(lr_clock_div);
616
617 RK_I2S_WRITE_4(sc, I2S_CKR, val);
618 }
619
620 return (speed);
621 }
622
623 static device_method_t rk_i2s_methods[] = {
624 /* Device interface */
625 DEVMETHOD(device_probe, rk_i2s_probe),
626 DEVMETHOD(device_attach, rk_i2s_attach),
627 DEVMETHOD(device_detach, rk_i2s_detach),
628
629 DEVMETHOD(audio_dai_init, rk_i2s_dai_init),
630 DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr),
631 DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk),
632 DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed),
633 DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat),
634 DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr),
635 DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps),
636 DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger),
637 DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr),
638
639 DEVMETHOD_END
640 };
641
642 static driver_t rk_i2s_driver = {
643 "i2s",
644 rk_i2s_methods,
645 sizeof(struct rk_i2s_softc),
646 };
647
648 DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, 0, 0);
649 SIMPLEBUS_PNP_INFO(compat_data);
650