Searched refs:EMUL (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 202 auto EMUL = RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW); in getEEWAndEMUL() local
205 return std::make_pair(EEW, *EMUL); in getEEWAndEMUL()
253 auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW); in getSchedClassID()
254 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW); in getSchedClassID()
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | RISCVTargetParser.cpp | 231 unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8; in getSameRatioLMUL() local
232 if (!isValidLMUL(EMUL, Fractional)) in getSameRatioLMUL()
234 return RISCVVType::encodeLMUL(EMUL, Fractional); in getSameRatioLMUL()
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| /freebsd/sys/powerpc/booke/ |
| H A D | spe.c | 203 #define EMUL 0x208 macro
360 case EMUL: in spe_emu_instr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrFormats.td | 73 // EMUL is at least 1. The destination vector register group cannot overlap
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| H A D | RISCVInstrInfoVPseudos.td | 20 /// LMUL/EMUL - Most instructions can write to differently sized register groups
2297 // * The destination EEW is greater than the source EEW, the source EMUL is
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| /freebsd/contrib/ncurses/misc/ |
| H A D | terminfo.src | 14296 # printer must be set to EMUL ANSI to accept ESC codes
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