1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __ECORE_HSI_ROCE__ 30 #define __ECORE_HSI_ROCE__ 31 /************************************************************************/ 32 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 33 /************************************************************************/ 34 #include "ecore_hsi_rdma.h" 35 /************************************************************************/ 36 /* Add include to common roce target for both eCore and protocol roce driver */ 37 /************************************************************************/ 38 #include "roce_common.h" 39 40 /* 41 * The roce storm context of Ystorm 42 */ 43 struct ystorm_roce_conn_st_ctx 44 { 45 struct regpair temp[2]; 46 }; 47 48 /* 49 * The roce storm context of Mstorm 50 */ 51 struct pstorm_roce_conn_st_ctx 52 { 53 struct regpair temp[16]; 54 }; 55 56 /* 57 * The roce storm context of Xstorm 58 */ 59 struct xstorm_roce_conn_st_ctx 60 { 61 struct regpair temp[24]; 62 }; 63 64 /* 65 * The roce storm context of Tstorm 66 */ 67 struct tstorm_roce_conn_st_ctx 68 { 69 struct regpair temp[30]; 70 }; 71 72 /* 73 * The roce storm context of Mstorm 74 */ 75 struct mstorm_roce_conn_st_ctx 76 { 77 struct regpair temp[6]; 78 }; 79 80 /* 81 * The roce storm context of Ystorm 82 */ 83 struct ustorm_roce_conn_st_ctx 84 { 85 struct regpair temp[12]; 86 }; 87 88 /* 89 * roce connection context 90 */ 91 struct e4_roce_conn_context 92 { 93 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 94 struct regpair ystorm_st_padding[2] /* padding */; 95 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 96 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 97 struct regpair xstorm_st_padding[2] /* padding */; 98 struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 99 struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 100 struct timers_context timer_context /* timer context */; 101 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 102 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 103 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 104 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 105 struct regpair ustorm_st_padding[2] /* padding */; 106 }; 107 108 /* 109 * roce connection context 110 */ 111 struct e5_roce_conn_context 112 { 113 struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 114 struct regpair ystorm_st_padding[2] /* padding */; 115 struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 116 struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 117 struct regpair xstorm_st_padding[2] /* padding */; 118 struct e5_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 119 struct e5_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 120 struct timers_context timer_context /* timer context */; 121 struct e5_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 122 struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 123 struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 124 struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 125 struct regpair ustorm_st_padding[2] /* padding */; 126 }; 127 128 /* 129 * roce create qp requester ramrod data 130 */ 131 struct roce_create_qp_req_ramrod_data 132 { 133 __le16 flags; 134 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 135 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 136 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 137 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 138 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 139 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 140 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 141 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 142 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 143 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 144 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 145 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 146 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 147 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 148 u8 max_ord; 149 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 150 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 151 u8 orq_num_pages; 152 __le16 p_key; 153 __le32 flow_label; 154 __le32 dst_qp_id; 155 __le32 ack_timeout_val; 156 __le32 initial_psn; 157 __le16 mtu; 158 __le16 pd; 159 __le16 sq_num_pages; 160 __le16 low_latency_phy_queue; 161 struct regpair sq_pbl_addr; 162 struct regpair orq_pbl_addr; 163 __le16 local_mac_addr[3] /* BE order */; 164 __le16 remote_mac_addr[3] /* BE order */; 165 __le16 vlan_id; 166 __le16 udp_src_port /* Only relevant in RRoCE */; 167 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 168 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 169 __le32 cq_cid; 170 struct regpair qp_handle_for_cqe; 171 struct regpair qp_handle_for_async; 172 u8 stats_counter_id /* Statistics counter ID to use */; 173 u8 reserved3[7]; 174 __le16 regular_latency_phy_queue; 175 __le16 dpi; 176 }; 177 178 /* 179 * roce create qp responder ramrod data 180 */ 181 struct roce_create_qp_resp_ramrod_data 182 { 183 __le32 flags; 184 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 185 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 186 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 187 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 188 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 189 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 190 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 191 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 192 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 193 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 194 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 195 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 196 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 197 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 198 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 199 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 200 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 201 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 202 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 203 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 204 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF 205 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17 206 __le16 xrc_domain /* SRC domain. Only applicable when xrc_flag is set */; 207 u8 max_ird; 208 u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 209 u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 210 u8 irq_num_pages; 211 __le16 p_key; 212 __le32 flow_label; 213 __le32 dst_qp_id; 214 u8 stats_counter_id /* Statistics counter ID to use */; 215 u8 reserved1; 216 __le16 mtu; 217 __le32 initial_psn; 218 __le16 pd; 219 __le16 rq_num_pages; 220 struct rdma_srq_id srq_id; 221 struct regpair rq_pbl_addr; 222 struct regpair irq_pbl_addr; 223 __le16 local_mac_addr[3] /* BE order */; 224 __le16 remote_mac_addr[3] /* BE order */; 225 __le16 vlan_id; 226 __le16 udp_src_port /* Only relevant in RRoCE */; 227 __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 228 __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 229 struct regpair qp_handle_for_cqe; 230 struct regpair qp_handle_for_async; 231 __le16 low_latency_phy_queue; 232 u8 reserved2[2]; 233 __le32 cq_cid; 234 __le16 regular_latency_phy_queue; 235 __le16 dpi; 236 }; 237 238 /* 239 * roce DCQCN received statistics 240 */ 241 struct roce_dcqcn_received_stats 242 { 243 struct regpair ecn_pkt_rcv /* The number of total packets with ECN indication received */; 244 struct regpair cnp_pkt_rcv /* The number of total RoCE packets with CNP opcode received */; 245 }; 246 247 /* 248 * roce DCQCN sent statistics 249 */ 250 struct roce_dcqcn_sent_stats 251 { 252 struct regpair cnp_pkt_sent /* The number of total RoCE packets with CNP opcode sent */; 253 }; 254 255 /* 256 * RoCE destroy qp requester output params 257 */ 258 struct roce_destroy_qp_req_output_params 259 { 260 __le32 num_bound_mw; 261 __le32 cq_prod /* Completion producer value at destroy QP */; 262 }; 263 264 /* 265 * RoCE destroy qp requester ramrod data 266 */ 267 struct roce_destroy_qp_req_ramrod_data 268 { 269 struct regpair output_params_addr; 270 }; 271 272 /* 273 * RoCE destroy qp responder output params 274 */ 275 struct roce_destroy_qp_resp_output_params 276 { 277 __le32 num_invalidated_mw; 278 __le32 cq_prod /* Completion producer value at destroy QP */; 279 }; 280 281 /* 282 * RoCE destroy qp responder ramrod data 283 */ 284 struct roce_destroy_qp_resp_ramrod_data 285 { 286 struct regpair output_params_addr; 287 }; 288 289 /* 290 * roce special events statistics 291 */ 292 struct roce_events_stats 293 { 294 __le16 silent_drops; 295 __le16 rnr_naks_sent; 296 __le32 retransmit_count; 297 __le32 icrc_error_count; 298 __le32 reserved; 299 }; 300 301 /* 302 * ROCE slow path EQ cmd IDs 303 */ 304 enum roce_event_opcode 305 { 306 ROCE_EVENT_CREATE_QP=11, 307 ROCE_EVENT_MODIFY_QP, 308 ROCE_EVENT_QUERY_QP, 309 ROCE_EVENT_DESTROY_QP, 310 ROCE_EVENT_CREATE_UD_QP, 311 ROCE_EVENT_DESTROY_UD_QP, 312 MAX_ROCE_EVENT_OPCODE 313 }; 314 315 /* 316 * roce func init ramrod data 317 */ 318 struct roce_init_func_params 319 { 320 u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */; 321 u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */; 322 u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */; 323 u8 reserved; 324 __le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */; 325 }; 326 327 /* 328 * roce func init ramrod data 329 */ 330 struct roce_init_func_ramrod_data 331 { 332 struct rdma_init_func_ramrod_data rdma; 333 struct roce_init_func_params roce; 334 }; 335 336 /* 337 * roce modify qp requester ramrod data 338 */ 339 struct roce_modify_qp_req_ramrod_data 340 { 341 __le16 flags; 342 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 343 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 344 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 345 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 346 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 347 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 348 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 349 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 350 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 351 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 352 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 353 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 354 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 355 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 356 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 357 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 358 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 359 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 360 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 361 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 362 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 363 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 364 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 365 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13 366 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 367 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 368 u8 fields; 369 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 370 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 371 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 372 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 373 u8 max_ord; 374 u8 traffic_class; 375 u8 hop_limit; 376 __le16 p_key; 377 __le32 flow_label; 378 __le32 ack_timeout_val; 379 __le16 mtu; 380 __le16 reserved2; 381 __le32 reserved3[2]; 382 __le16 low_latency_phy_queue; 383 __le16 regular_latency_phy_queue; 384 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 385 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 386 }; 387 388 /* 389 * roce modify qp responder ramrod data 390 */ 391 struct roce_modify_qp_resp_ramrod_data 392 { 393 __le16 flags; 394 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 395 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 396 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 397 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 398 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 399 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 400 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 401 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 402 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 403 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 404 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 405 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 406 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 407 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 408 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 409 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 410 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 411 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 412 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 413 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 414 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 415 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10 416 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F 417 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 418 u8 fields; 419 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 420 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 421 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 422 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 423 u8 max_ird; 424 u8 traffic_class; 425 u8 hop_limit; 426 __le16 p_key; 427 __le32 flow_label; 428 __le16 mtu; 429 __le16 low_latency_phy_queue; 430 __le16 regular_latency_phy_queue; 431 u8 reserved2[6]; 432 __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 433 __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 434 }; 435 436 /* 437 * RoCE query qp requester output params 438 */ 439 struct roce_query_qp_req_output_params 440 { 441 __le32 psn /* send next psn */; 442 __le32 flags; 443 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 444 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 445 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 446 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 447 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 448 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 449 }; 450 451 /* 452 * RoCE query qp requester ramrod data 453 */ 454 struct roce_query_qp_req_ramrod_data 455 { 456 struct regpair output_params_addr; 457 }; 458 459 /* 460 * RoCE query qp responder output params 461 */ 462 struct roce_query_qp_resp_output_params 463 { 464 __le32 psn /* send next psn */; 465 __le32 err_flag; 466 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 467 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 468 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 469 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 470 }; 471 472 /* 473 * RoCE query qp responder ramrod data 474 */ 475 struct roce_query_qp_resp_ramrod_data 476 { 477 struct regpair output_params_addr; 478 }; 479 480 /* 481 * ROCE ramrod command IDs 482 */ 483 enum roce_ramrod_cmd_id 484 { 485 ROCE_RAMROD_CREATE_QP=11, 486 ROCE_RAMROD_MODIFY_QP, 487 ROCE_RAMROD_QUERY_QP, 488 ROCE_RAMROD_DESTROY_QP, 489 ROCE_RAMROD_CREATE_UD_QP, 490 ROCE_RAMROD_DESTROY_UD_QP, 491 MAX_ROCE_RAMROD_CMD_ID 492 }; 493 494 struct e4_mstorm_roce_req_conn_ag_ctx 495 { 496 u8 byte0 /* cdu_validation */; 497 u8 byte1 /* state */; 498 u8 flags0; 499 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 500 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 501 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 502 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 503 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 504 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 505 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 506 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 507 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 508 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 509 u8 flags1; 510 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 511 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 512 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 513 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 514 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 515 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 516 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 517 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 518 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 519 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 520 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 521 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 522 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 523 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 524 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 525 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 526 __le16 word0 /* word0 */; 527 __le16 word1 /* word1 */; 528 __le32 reg0 /* reg0 */; 529 __le32 reg1 /* reg1 */; 530 }; 531 532 struct e4_mstorm_roce_resp_conn_ag_ctx 533 { 534 u8 byte0 /* cdu_validation */; 535 u8 byte1 /* state */; 536 u8 flags0; 537 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 538 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 539 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 540 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 541 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 542 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 543 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 544 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 545 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 546 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 547 u8 flags1; 548 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 549 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 550 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 551 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 552 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 553 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 554 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 555 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 556 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 557 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 558 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 559 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 560 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 561 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 562 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 563 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 564 __le16 word0 /* word0 */; 565 __le16 word1 /* word1 */; 566 __le32 reg0 /* reg0 */; 567 __le32 reg1 /* reg1 */; 568 }; 569 570 struct e4_tstorm_roce_req_conn_ag_ctx 571 { 572 u8 reserved0 /* cdu_validation */; 573 u8 state /* state */; 574 u8 flags0; 575 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 576 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 577 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 578 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 579 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 580 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 581 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 582 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 583 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 584 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 585 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 586 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 587 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 588 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 589 u8 flags1; 590 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 591 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 592 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 593 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 594 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 595 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 596 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 597 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 598 u8 flags2; 599 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 600 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 601 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 602 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 603 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 604 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 605 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 606 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 607 u8 flags3; 608 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 609 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 610 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 611 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 612 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 613 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 614 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 615 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 616 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 617 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 619 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 620 u8 flags4; 621 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 622 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 623 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 624 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 625 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 626 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 627 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 628 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 629 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 630 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 631 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 632 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 633 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 634 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 635 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 636 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 637 u8 flags5; 638 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 639 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 640 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 641 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 642 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 643 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 644 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 645 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 646 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 647 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 648 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 649 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 650 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 651 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 652 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 653 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 654 __le32 reg0 /* reg0 */; 655 __le32 snd_nxt_psn /* reg1 */; 656 __le32 snd_max_psn /* reg2 */; 657 __le32 orq_prod /* reg3 */; 658 __le32 reg4 /* reg4 */; 659 __le32 reg5 /* reg5 */; 660 __le32 reg6 /* reg6 */; 661 __le32 reg7 /* reg7 */; 662 __le32 reg8 /* reg8 */; 663 u8 tx_cqe_error_type /* byte2 */; 664 u8 orq_cache_idx /* byte3 */; 665 __le16 snd_sq_cons_th /* word0 */; 666 u8 byte4 /* byte4 */; 667 u8 byte5 /* byte5 */; 668 __le16 snd_sq_cons /* word1 */; 669 __le16 conn_dpi /* conn_dpi */; 670 __le16 word3 /* word3 */; 671 __le32 reg9 /* reg9 */; 672 __le32 reg10 /* reg10 */; 673 }; 674 675 struct e4_tstorm_roce_resp_conn_ag_ctx 676 { 677 u8 byte0 /* cdu_validation */; 678 u8 state /* state */; 679 u8 flags0; 680 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 681 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 682 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 683 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 684 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 685 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 686 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 687 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 688 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 689 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 690 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 691 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 692 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 693 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 694 u8 flags1; 695 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 696 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 697 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 698 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 699 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 700 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 701 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 702 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 703 u8 flags2; 704 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 705 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 706 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 707 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 708 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 709 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 710 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 711 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 712 u8 flags3; 713 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 714 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 715 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 716 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 717 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 718 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 719 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 720 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 721 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 722 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 723 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 724 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 725 u8 flags4; 726 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 727 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 728 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 729 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 730 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 731 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 732 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 733 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 734 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 735 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 736 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 737 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 738 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 739 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 740 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 741 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 742 u8 flags5; 743 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 744 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 745 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 746 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 747 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 748 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 749 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 750 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 751 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 752 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 753 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 754 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 755 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 756 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 757 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 758 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 759 __le32 psn_and_rxmit_id_echo /* reg0 */; 760 __le32 reg1 /* reg1 */; 761 __le32 reg2 /* reg2 */; 762 __le32 reg3 /* reg3 */; 763 __le32 reg4 /* reg4 */; 764 __le32 reg5 /* reg5 */; 765 __le32 reg6 /* reg6 */; 766 __le32 reg7 /* reg7 */; 767 __le32 reg8 /* reg8 */; 768 u8 tx_async_error_type /* byte2 */; 769 u8 byte3 /* byte3 */; 770 __le16 rq_cons /* word0 */; 771 u8 byte4 /* byte4 */; 772 u8 byte5 /* byte5 */; 773 __le16 rq_prod /* word1 */; 774 __le16 conn_dpi /* conn_dpi */; 775 __le16 irq_cons /* word3 */; 776 __le32 num_invlidated_mw /* reg9 */; 777 __le32 reg10 /* reg10 */; 778 }; 779 780 struct e4_ustorm_roce_req_conn_ag_ctx 781 { 782 u8 byte0 /* cdu_validation */; 783 u8 byte1 /* state */; 784 u8 flags0; 785 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 786 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 787 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 788 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 789 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 790 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 791 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 792 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 793 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 794 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 795 u8 flags1; 796 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 797 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 798 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 799 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 800 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 801 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 802 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 803 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 804 u8 flags2; 805 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 806 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 807 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 808 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 809 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 810 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 811 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 812 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 813 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 814 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 815 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 816 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 817 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 818 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 819 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 820 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 821 u8 flags3; 822 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 823 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 824 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 825 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 826 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 827 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 828 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 829 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 830 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 831 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 832 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 833 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 834 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 835 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 836 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 837 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 838 u8 byte2 /* byte2 */; 839 u8 byte3 /* byte3 */; 840 __le16 word0 /* conn_dpi */; 841 __le16 word1 /* word1 */; 842 __le32 reg0 /* reg0 */; 843 __le32 reg1 /* reg1 */; 844 __le32 reg2 /* reg2 */; 845 __le32 reg3 /* reg3 */; 846 __le16 word2 /* word2 */; 847 __le16 word3 /* word3 */; 848 }; 849 850 struct e4_ustorm_roce_resp_conn_ag_ctx 851 { 852 u8 byte0 /* cdu_validation */; 853 u8 byte1 /* state */; 854 u8 flags0; 855 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 856 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 857 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 858 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 859 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 860 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 861 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 862 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 863 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 864 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 865 u8 flags1; 866 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 867 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 868 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 869 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 870 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 871 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 872 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 873 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 874 u8 flags2; 875 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 876 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 877 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 878 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 879 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 880 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 881 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 882 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 883 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 884 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 885 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 886 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 887 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 888 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 889 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 890 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 891 u8 flags3; 892 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 893 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 894 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 895 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 896 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 897 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 898 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 899 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 900 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 901 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 902 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 903 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 904 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 905 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 906 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 907 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 908 u8 byte2 /* byte2 */; 909 u8 byte3 /* byte3 */; 910 __le16 word0 /* conn_dpi */; 911 __le16 word1 /* word1 */; 912 __le32 reg0 /* reg0 */; 913 __le32 reg1 /* reg1 */; 914 __le32 reg2 /* reg2 */; 915 __le32 reg3 /* reg3 */; 916 __le16 word2 /* word2 */; 917 __le16 word3 /* word3 */; 918 }; 919 920 struct e4_xstorm_roce_req_conn_ag_ctx 921 { 922 u8 reserved0 /* cdu_validation */; 923 u8 state /* state */; 924 u8 flags0; 925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 926 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 941 u8 flags1; 942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 943 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 958 u8 flags2; 959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 960 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 967 u8 flags3; 968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 969 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 976 u8 flags4; 977 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 978 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 985 u8 flags5; 986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 987 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 990 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 993 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 994 u8 flags6; 995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 996 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 997 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 1001 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1002 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 1003 u8 flags7; 1004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1005 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 1006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1007 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 1008 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1009 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1010 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1011 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 1012 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1013 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 1014 u8 flags8; 1015 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1016 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 1017 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1018 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 1019 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1020 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 1021 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1022 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1023 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1024 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 1025 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1026 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1027 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1028 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 1029 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1030 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 1031 u8 flags9; 1032 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1033 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 1034 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1035 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 1036 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1037 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 1038 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1039 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 1040 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1041 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 1042 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1043 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 1044 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1045 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 1046 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1047 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 1048 u8 flags10; 1049 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1050 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 1051 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1052 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 1053 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1054 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 1055 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1056 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 1057 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1058 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1059 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1060 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 1061 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1062 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 1063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 1065 u8 flags11; 1066 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1067 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 1068 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1069 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 1070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 1072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1073 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 1074 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1075 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 1076 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1077 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 1078 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1079 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1080 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1081 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 1082 u8 flags12; 1083 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1084 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 1085 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1086 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 1087 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1088 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1089 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1090 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1091 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1092 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 1093 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1094 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 1095 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1096 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 1097 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1098 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 1099 u8 flags13; 1100 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1101 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 1102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1103 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 1104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1109 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1112 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1113 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1114 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1115 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1116 u8 flags14; 1117 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1118 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 1119 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1120 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 1121 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1122 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1123 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1124 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 1125 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1126 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1127 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1128 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 1129 u8 byte2 /* byte2 */; 1130 __le16 physical_q0 /* physical_q0 */; 1131 __le16 word1 /* physical_q1 */; 1132 __le16 sq_cmp_cons /* physical_q2 */; 1133 __le16 sq_cons /* word3 */; 1134 __le16 sq_prod /* word4 */; 1135 __le16 word5 /* word5 */; 1136 __le16 conn_dpi /* conn_dpi */; 1137 u8 byte3 /* byte3 */; 1138 u8 byte4 /* byte4 */; 1139 u8 byte5 /* byte5 */; 1140 u8 byte6 /* byte6 */; 1141 __le32 lsn /* reg0 */; 1142 __le32 ssn /* reg1 */; 1143 __le32 snd_una_psn /* reg2 */; 1144 __le32 snd_nxt_psn /* reg3 */; 1145 __le32 reg4 /* reg4 */; 1146 __le32 orq_cons_th /* cf_array0 */; 1147 __le32 orq_cons /* cf_array1 */; 1148 }; 1149 1150 struct e4_xstorm_roce_resp_conn_ag_ctx 1151 { 1152 u8 reserved0 /* cdu_validation */; 1153 u8 state /* state */; 1154 u8 flags0; 1155 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 1159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 1161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 1165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 1166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 1167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 1169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 1171 u8 flags1; 1172 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 1174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 1176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 1178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 1180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 1182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 1184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 1185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 1186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1188 u8 flags2; 1189 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1190 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 1191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 1193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 1195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 1197 u8 flags3; 1198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 1199 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 1200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 1202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 1203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 1204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1206 u8 flags4; 1207 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1208 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 1209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 1211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 1213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 1215 u8 flags5; 1216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1217 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 1218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 1220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1221 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 1222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1223 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 1224 u8 flags6; 1225 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1226 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 1227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1228 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 1229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 1231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1232 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 1233 u8 flags7; 1234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1235 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 1236 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 1238 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1239 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1240 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1241 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 1242 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1243 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 1244 u8 flags8; 1245 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1246 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 1247 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1248 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 1249 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 1250 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 1251 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1252 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1253 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 1254 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 1255 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1256 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1257 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1258 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 1259 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1260 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 1261 u8 flags9; 1262 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1263 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 1264 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1265 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 1266 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1267 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 1268 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1269 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 1270 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1271 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 1272 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1273 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 1274 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1275 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 1276 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1277 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 1278 u8 flags10; 1279 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1280 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 1281 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1282 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 1283 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1284 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 1285 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1286 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 1287 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1288 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1289 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1290 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 1291 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 1293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 1295 u8 flags11; 1296 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1297 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 1298 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 1300 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 1302 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1303 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 1304 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1305 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 1306 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1307 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 1308 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1309 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1310 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1311 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 1312 u8 flags12; 1313 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule10en */ 1314 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 1315 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1316 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 1317 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1318 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1319 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1320 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1321 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1322 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 1323 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1324 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 1325 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1326 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 1327 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 1329 u8 flags13; 1330 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1331 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 1332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 1334 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1338 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1344 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1345 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1346 u8 flags14; 1347 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1348 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 1349 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1350 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 1351 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 1352 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 1353 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 1354 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 1355 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1356 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 1357 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 1358 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 1359 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1360 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 1361 u8 byte2 /* byte2 */; 1362 __le16 physical_q0 /* physical_q0 */; 1363 __le16 irq_prod_shadow /* physical_q1 */; 1364 __le16 word2 /* physical_q2 */; 1365 __le16 irq_cons /* word3 */; 1366 __le16 irq_prod /* word4 */; 1367 __le16 e5_reserved1 /* word5 */; 1368 __le16 conn_dpi /* conn_dpi */; 1369 u8 rxmit_opcode /* byte3 */; 1370 u8 byte4 /* byte4 */; 1371 u8 byte5 /* byte5 */; 1372 u8 byte6 /* byte6 */; 1373 __le32 rxmit_psn_and_id /* reg0 */; 1374 __le32 rxmit_bytes_length /* reg1 */; 1375 __le32 psn /* reg2 */; 1376 __le32 reg3 /* reg3 */; 1377 __le32 reg4 /* reg4 */; 1378 __le32 reg5 /* cf_array0 */; 1379 __le32 msn_and_syndrome /* cf_array1 */; 1380 }; 1381 1382 struct e4_ystorm_roce_req_conn_ag_ctx 1383 { 1384 u8 byte0 /* cdu_validation */; 1385 u8 byte1 /* state */; 1386 u8 flags0; 1387 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1388 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1389 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1390 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1391 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1392 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1393 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1394 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1395 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1396 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1397 u8 flags1; 1398 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1399 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1400 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1401 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1402 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1403 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1404 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1405 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1406 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1407 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1408 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1409 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1410 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1411 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1412 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1413 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1414 u8 byte2 /* byte2 */; 1415 u8 byte3 /* byte3 */; 1416 __le16 word0 /* word0 */; 1417 __le32 reg0 /* reg0 */; 1418 __le32 reg1 /* reg1 */; 1419 __le16 word1 /* word1 */; 1420 __le16 word2 /* word2 */; 1421 __le16 word3 /* word3 */; 1422 __le16 word4 /* word4 */; 1423 __le32 reg2 /* reg2 */; 1424 __le32 reg3 /* reg3 */; 1425 }; 1426 1427 struct e4_ystorm_roce_resp_conn_ag_ctx 1428 { 1429 u8 byte0 /* cdu_validation */; 1430 u8 byte1 /* state */; 1431 u8 flags0; 1432 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1433 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1434 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1435 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1436 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1437 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1438 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1439 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1440 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1441 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1442 u8 flags1; 1443 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1444 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1445 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1446 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1447 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1448 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1449 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1450 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1451 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1452 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1453 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1454 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1455 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1456 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1457 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1458 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1459 u8 byte2 /* byte2 */; 1460 u8 byte3 /* byte3 */; 1461 __le16 word0 /* word0 */; 1462 __le32 reg0 /* reg0 */; 1463 __le32 reg1 /* reg1 */; 1464 __le16 word1 /* word1 */; 1465 __le16 word2 /* word2 */; 1466 __le16 word3 /* word3 */; 1467 __le16 word4 /* word4 */; 1468 __le32 reg2 /* reg2 */; 1469 __le32 reg3 /* reg3 */; 1470 }; 1471 1472 struct E5XstormRoceConnAgCtxDqExtLdPart 1473 { 1474 u8 reserved0 /* cdu_validation */; 1475 u8 state_and_core_id /* state_and_core_id */; 1476 u8 flags0; 1477 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1478 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1479 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1480 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1481 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1482 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1483 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1484 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1485 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1486 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1487 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1488 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1489 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1490 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1491 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1492 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1493 u8 flags1; 1494 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1495 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1496 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1497 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1498 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 1499 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 1500 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1501 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1502 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 1503 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1504 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */ 1505 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1506 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_MASK 0x1 /* bit14 */ 1507 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_SHIFT 6 1508 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1509 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 1510 u8 flags2; 1511 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1512 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1513 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1514 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1515 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1516 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1517 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1518 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1519 u8 flags3; 1520 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 1521 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_SHIFT 0 1522 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1523 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_SHIFT 2 1524 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 1525 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_SHIFT 4 1526 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1527 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 1528 u8 flags4; 1529 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1530 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1531 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1532 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1533 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1534 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1535 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1536 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1537 u8 flags5; 1538 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1539 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1540 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1541 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1542 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 1543 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_SHIFT 4 1544 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1545 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1546 u8 flags6; 1547 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 1548 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 1549 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 1550 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 1551 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 1552 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 1553 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 1554 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 1555 u8 flags7; 1556 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 1557 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 1558 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 1559 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 1560 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1561 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1562 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1563 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1564 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1565 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1566 u8 flags8; 1567 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1568 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1569 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1570 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1571 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1572 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_SHIFT 2 1573 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1574 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_SHIFT 3 1575 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1576 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_SHIFT 4 1577 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1578 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 1579 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1580 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1581 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1582 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1583 u8 flags9; 1584 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1585 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1586 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1587 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1588 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1589 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1590 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1591 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1592 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1593 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_SHIFT 4 1594 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1595 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1596 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 1597 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 1598 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1599 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 1600 u8 flags10; 1601 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 1602 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 1603 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 1604 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 1605 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 1606 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 1607 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 1608 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 1609 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1610 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1611 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 1612 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 1613 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 1614 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 1615 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 1616 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 1617 u8 flags11; 1618 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 1619 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 1620 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 1621 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 1622 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 1623 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 1624 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1625 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1626 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1627 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1628 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1629 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_SHIFT 5 1630 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1631 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1632 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1633 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1634 u8 flags12; 1635 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1636 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_SHIFT 0 1637 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1638 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1639 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1640 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1641 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1642 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1643 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1644 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_SHIFT 4 1645 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1646 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1647 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1648 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_SHIFT 6 1649 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1650 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_SHIFT 7 1651 u8 flags13; 1652 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1653 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1654 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1655 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1656 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1657 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1658 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1659 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1660 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1661 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1662 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1663 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1664 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1665 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1666 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1667 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1668 u8 flags14; 1669 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1670 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_SHIFT 0 1671 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 1672 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 1673 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1674 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 1675 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 1676 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 1677 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1678 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1679 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 1680 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 1681 u8 byte2 /* byte2 */; 1682 __le16 physical_q0 /* physical_q0 */; 1683 __le16 word1 /* physical_q1 */; 1684 __le16 sq_cmp_cons /* physical_q2 */; 1685 __le16 sq_cons /* word3 */; 1686 __le16 sq_prod /* word4 */; 1687 __le16 word5 /* word5 */; 1688 __le16 conn_dpi /* conn_dpi */; 1689 u8 byte3 /* byte3 */; 1690 u8 byte4 /* byte4 */; 1691 u8 byte5 /* byte5 */; 1692 u8 byte6 /* byte6 */; 1693 __le32 lsn /* reg0 */; 1694 __le32 ssn /* reg1 */; 1695 __le32 snd_una_psn /* reg2 */; 1696 __le32 snd_nxt_psn /* reg3 */; 1697 __le32 reg4 /* reg4 */; 1698 __le32 orq_cons_th /* cf_array0 */; 1699 __le32 orq_cons /* cf_array1 */; 1700 u8 flags15; 1701 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_MASK 0x1 /* bit22 */ 1702 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_SHIFT 0 1703 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_MASK 0x1 /* bit23 */ 1704 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_SHIFT 1 1705 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_MASK 0x1 /* bit24 */ 1706 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_SHIFT 2 1707 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_MASK 0x3 /* cf24 */ 1708 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_SHIFT 3 1709 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_MASK 0x1 /* cf24en */ 1710 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_SHIFT 5 1711 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_MASK 0x1 /* rule26en */ 1712 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_SHIFT 6 1713 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_MASK 0x1 /* rule27en */ 1714 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_SHIFT 7 1715 u8 byte7 /* byte7 */; 1716 __le16 word7 /* word7 */; 1717 __le16 word8 /* word8 */; 1718 __le16 word9 /* word9 */; 1719 __le16 word10 /* word10 */; 1720 __le16 tx_rdma_edpm_usg_cnt /* word11 */; 1721 __le32 reg7 /* reg7 */; 1722 __le32 reg8 /* reg8 */; 1723 __le32 reg9 /* reg9 */; 1724 u8 byte8 /* byte8 */; 1725 u8 byte9 /* byte9 */; 1726 u8 byte10 /* byte10 */; 1727 u8 byte11 /* byte11 */; 1728 u8 byte12 /* byte12 */; 1729 u8 byte13 /* byte13 */; 1730 u8 byte14 /* byte14 */; 1731 u8 byte15 /* byte15 */; 1732 __le32 reg10 /* reg10 */; 1733 __le32 reg11 /* reg11 */; 1734 __le32 reg12 /* reg12 */; 1735 __le32 reg13 /* reg13 */; 1736 }; 1737 1738 struct e5_mstorm_roce_req_conn_ag_ctx 1739 { 1740 u8 byte0 /* cdu_validation */; 1741 u8 byte1 /* state_and_core_id */; 1742 u8 flags0; 1743 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1744 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1745 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1746 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1747 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1748 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1749 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1750 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1751 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1752 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1753 u8 flags1; 1754 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1755 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1756 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1757 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1758 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1759 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1760 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1761 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1762 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1763 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1764 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1765 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1766 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1767 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1768 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1769 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1770 __le16 word0 /* word0 */; 1771 __le16 word1 /* word1 */; 1772 __le32 reg0 /* reg0 */; 1773 __le32 reg1 /* reg1 */; 1774 }; 1775 1776 struct e5_mstorm_roce_resp_conn_ag_ctx 1777 { 1778 u8 byte0 /* cdu_validation */; 1779 u8 byte1 /* state_and_core_id */; 1780 u8 flags0; 1781 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1782 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1783 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1784 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1785 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1786 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1787 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1788 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1789 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1790 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1791 u8 flags1; 1792 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1793 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1794 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1795 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1796 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1797 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1798 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1799 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1800 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1801 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1802 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1803 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1804 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1805 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1806 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1807 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1808 __le16 word0 /* word0 */; 1809 __le16 word1 /* word1 */; 1810 __le32 reg0 /* reg0 */; 1811 __le32 reg1 /* reg1 */; 1812 }; 1813 1814 struct e5_tstorm_roce_req_conn_ag_ctx 1815 { 1816 u8 reserved0 /* cdu_validation */; 1817 u8 state_and_core_id /* state_and_core_id */; 1818 u8 flags0; 1819 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1820 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1821 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 1822 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 1823 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 1824 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 1825 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1826 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 1827 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1828 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1829 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 1830 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 1831 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 1832 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 1833 u8 flags1; 1834 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1835 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 1836 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 1837 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 1838 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1839 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1840 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1841 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1842 u8 flags2; 1843 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1844 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1845 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 1846 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 1847 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 1848 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 1849 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 1850 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 1851 u8 flags3; 1852 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 1853 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 1854 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 1855 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 1856 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1857 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 1858 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1859 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 1860 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 1861 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 1862 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1863 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1864 u8 flags4; 1865 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1866 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1867 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1868 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1869 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 1870 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 1871 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 1872 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 1873 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 1874 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 1875 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 1876 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 1877 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 1878 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 1879 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1880 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 1881 u8 flags5; 1882 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1883 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 1884 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1885 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 1886 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1887 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 1888 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1889 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 1890 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1891 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 1892 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 1893 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 1894 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1895 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 1896 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1897 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 1898 u8 flags6; 1899 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1900 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1901 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1902 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1903 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1904 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1905 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1906 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1907 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1908 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1909 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1910 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1911 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1912 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1913 u8 tx_cqe_error_type /* byte2 */; 1914 __le16 snd_sq_cons_th /* word0 */; 1915 __le32 reg0 /* reg0 */; 1916 __le32 snd_nxt_psn /* reg1 */; 1917 __le32 snd_max_psn /* reg2 */; 1918 __le32 orq_prod /* reg3 */; 1919 __le32 reg4 /* reg4 */; 1920 __le32 reg5 /* reg5 */; 1921 __le32 reg6 /* reg6 */; 1922 __le32 reg7 /* reg7 */; 1923 __le32 reg8 /* reg8 */; 1924 u8 orq_cache_idx /* byte3 */; 1925 u8 byte4 /* byte4 */; 1926 u8 byte5 /* byte5 */; 1927 u8 e4_reserved8 /* byte6 */; 1928 __le16 snd_sq_cons /* word1 */; 1929 __le16 word2 /* conn_dpi */; 1930 __le32 reg9 /* reg9 */; 1931 __le16 word3 /* word3 */; 1932 __le16 e4_reserved9 /* word4 */; 1933 }; 1934 1935 struct e5_tstorm_roce_resp_conn_ag_ctx 1936 { 1937 u8 byte0 /* cdu_validation */; 1938 u8 state_and_core_id /* state_and_core_id */; 1939 u8 flags0; 1940 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1941 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1942 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 1943 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 1944 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1945 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 1946 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1947 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 1948 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1949 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1950 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1951 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 1952 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1953 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 1954 u8 flags1; 1955 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 1956 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 1957 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 1958 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 1959 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1960 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 1961 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1962 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1963 u8 flags2; 1964 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1965 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1966 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1967 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 1968 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1969 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 1970 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1971 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 1972 u8 flags3; 1973 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1974 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 1975 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1976 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 1977 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1978 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 1979 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 1980 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 1981 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 1982 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 1983 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1984 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 1985 u8 flags4; 1986 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1987 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1988 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1989 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1990 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1991 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 1992 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1993 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 1994 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1995 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 1996 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1997 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 1998 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1999 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 2000 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2001 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2002 u8 flags5; 2003 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2004 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2005 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2006 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2007 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2008 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2009 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2010 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2011 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2012 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2013 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 2014 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 2015 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2016 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2017 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2018 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2019 u8 flags6; 2020 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 2021 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2022 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 2023 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2024 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 2025 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2026 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 2027 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2028 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 2029 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2030 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 2031 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2032 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 2033 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2034 u8 tx_async_error_type /* byte2 */; 2035 __le16 rq_cons /* word0 */; 2036 __le32 psn_and_rxmit_id_echo /* reg0 */; 2037 __le32 reg1 /* reg1 */; 2038 __le32 reg2 /* reg2 */; 2039 __le32 reg3 /* reg3 */; 2040 __le32 reg4 /* reg4 */; 2041 __le32 reg5 /* reg5 */; 2042 __le32 reg6 /* reg6 */; 2043 __le32 reg7 /* reg7 */; 2044 __le32 reg8 /* reg8 */; 2045 u8 byte3 /* byte3 */; 2046 u8 byte4 /* byte4 */; 2047 u8 byte5 /* byte5 */; 2048 u8 e4_reserved8 /* byte6 */; 2049 __le16 rq_prod /* word1 */; 2050 __le16 conn_dpi /* conn_dpi */; 2051 __le32 num_invlidated_mw /* reg9 */; 2052 __le16 irq_cons /* word3 */; 2053 __le16 e4_reserved9 /* word4 */; 2054 }; 2055 2056 struct e5_ustorm_roce_req_conn_ag_ctx 2057 { 2058 u8 byte0 /* cdu_validation */; 2059 u8 byte1 /* state_and_core_id */; 2060 u8 flags0; 2061 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2062 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2063 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2064 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2065 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2066 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2067 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2068 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2069 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2070 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2071 u8 flags1; 2072 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2073 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 2074 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2075 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 2076 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2077 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 2078 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2079 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 2080 u8 flags2; 2081 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2082 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2083 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2084 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2085 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2086 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2087 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2088 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 2089 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2090 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 2091 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2092 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 2093 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2094 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 2095 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2096 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 2097 u8 flags3; 2098 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2099 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 2100 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2101 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 2102 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2103 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 2104 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2105 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 2106 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2107 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 2108 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2109 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 2110 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2111 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 2112 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2113 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 2114 u8 flags4; 2115 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2116 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2117 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2118 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2119 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2120 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2121 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2122 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2123 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2124 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2125 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2126 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2127 u8 byte2 /* byte2 */; 2128 __le16 word0 /* conn_dpi */; 2129 __le16 word1 /* word1 */; 2130 __le32 reg0 /* reg0 */; 2131 __le32 reg1 /* reg1 */; 2132 __le32 reg2 /* reg2 */; 2133 __le32 reg3 /* reg3 */; 2134 __le16 word2 /* word2 */; 2135 __le16 word3 /* word3 */; 2136 }; 2137 2138 struct e5_ustorm_roce_resp_conn_ag_ctx 2139 { 2140 u8 byte0 /* cdu_validation */; 2141 u8 byte1 /* state_and_core_id */; 2142 u8 flags0; 2143 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2144 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2145 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2146 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2147 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2148 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2149 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2150 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2151 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2152 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2153 u8 flags1; 2154 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2155 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 2156 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2157 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 2158 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2159 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 2160 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2161 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 2162 u8 flags2; 2163 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2164 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2165 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2166 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2167 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2168 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2169 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2170 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 2171 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2172 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 2173 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2174 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 2175 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2176 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 2177 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2178 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2179 u8 flags3; 2180 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2181 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2182 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2183 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2184 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2185 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2186 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2187 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2188 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2189 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2190 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2191 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 2192 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2193 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2194 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2195 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2196 u8 flags4; 2197 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2198 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2199 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2200 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2201 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2202 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2203 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2204 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2205 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2206 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2207 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2208 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2209 u8 byte2 /* byte2 */; 2210 __le16 word0 /* conn_dpi */; 2211 __le16 word1 /* word1 */; 2212 __le32 reg0 /* reg0 */; 2213 __le32 reg1 /* reg1 */; 2214 __le32 reg2 /* reg2 */; 2215 __le32 reg3 /* reg3 */; 2216 __le16 word2 /* word2 */; 2217 __le16 word3 /* word3 */; 2218 }; 2219 2220 struct e5_xstorm_roce_req_conn_ag_ctx 2221 { 2222 u8 reserved0 /* cdu_validation */; 2223 u8 state_and_core_id /* state_and_core_id */; 2224 u8 flags0; 2225 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2226 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2227 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2228 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 2229 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2230 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 2231 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2232 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2233 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2234 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 2235 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2236 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 2237 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2238 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 2239 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2240 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 2241 u8 flags1; 2242 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2243 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 2244 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2245 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 2246 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2247 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 2248 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2249 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 2250 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2251 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 2252 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2253 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 2254 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2255 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2256 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2257 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2258 u8 flags2; 2259 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2260 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 2261 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2262 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 2263 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2264 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 2265 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2266 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 2267 u8 flags3; 2268 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 2269 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 2270 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2271 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2272 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 2273 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 2274 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2275 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2276 u8 flags4; 2277 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2278 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 2279 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2280 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 2281 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2282 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 2283 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2284 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 2285 u8 flags5; 2286 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2287 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 2288 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2289 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 2290 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 2291 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 2292 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2293 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 2294 u8 flags6; 2295 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2296 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 2297 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2298 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 2299 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2300 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 2301 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2302 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 2303 u8 flags7; 2304 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2305 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 2306 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2307 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 2308 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2309 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2310 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2311 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 2312 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2313 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 2314 u8 flags8; 2315 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2316 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 2317 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2318 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 2319 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 2320 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 2321 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2322 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2323 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 2324 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 2325 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2326 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2327 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2328 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 2329 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2330 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 2331 u8 flags9; 2332 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2333 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 2334 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2335 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 2336 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2337 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 2338 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2339 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 2340 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 2341 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 2342 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2343 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 2344 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2345 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 2346 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2347 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 2348 u8 flags10; 2349 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2350 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 2351 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2352 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 2353 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2354 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 2355 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2356 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 2357 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2358 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2359 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2360 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 2361 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2362 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 2363 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2364 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 2365 u8 flags11; 2366 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2367 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 2368 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2369 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 2370 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2371 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 2372 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2373 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 2374 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2375 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 2376 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 2377 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 2378 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2379 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2380 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2381 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 2382 u8 flags12; 2383 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 2384 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 2385 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2386 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 2387 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2388 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2389 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2390 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2391 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 2392 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 2393 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2394 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 2395 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 2396 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 2397 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 2398 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 2399 u8 flags13; 2400 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2401 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 2402 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2403 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 2404 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2405 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2406 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2407 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2408 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2409 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2410 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2411 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2412 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2413 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2414 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2415 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2416 u8 flags14; 2417 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 2418 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 2419 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2420 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 2421 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2422 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2423 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2424 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 2425 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2426 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2427 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2428 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 2429 u8 byte2 /* byte2 */; 2430 __le16 physical_q0 /* physical_q0 */; 2431 __le16 word1 /* physical_q1 */; 2432 __le16 sq_cmp_cons /* physical_q2 */; 2433 __le16 sq_cons /* word3 */; 2434 __le16 sq_prod /* word4 */; 2435 __le16 word5 /* word5 */; 2436 __le16 conn_dpi /* conn_dpi */; 2437 u8 byte3 /* byte3 */; 2438 u8 byte4 /* byte4 */; 2439 u8 byte5 /* byte5 */; 2440 u8 byte6 /* byte6 */; 2441 __le32 lsn /* reg0 */; 2442 __le32 ssn /* reg1 */; 2443 __le32 snd_una_psn /* reg2 */; 2444 __le32 snd_nxt_psn /* reg3 */; 2445 __le32 reg4 /* reg4 */; 2446 __le32 orq_cons_th /* cf_array0 */; 2447 __le32 orq_cons /* cf_array1 */; 2448 }; 2449 2450 struct e5_xstorm_roce_resp_conn_ag_ctx 2451 { 2452 u8 reserved0 /* cdu_validation */; 2453 u8 state_and_core_id /* state_and_core_id */; 2454 u8 flags0; 2455 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2456 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2457 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2458 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 2459 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2460 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 2461 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2462 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2463 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2464 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 2465 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2466 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 2467 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2468 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 2469 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2470 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 2471 u8 flags1; 2472 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2473 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 2474 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2475 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 2476 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2477 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 2478 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2479 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 2480 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2481 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 2482 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2483 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 2484 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2485 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2486 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2487 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2488 u8 flags2; 2489 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2490 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 2491 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2492 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 2493 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2494 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 2495 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2496 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 2497 u8 flags3; 2498 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 2499 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 2500 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2501 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2502 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 2503 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 2504 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2505 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2506 u8 flags4; 2507 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2508 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 2509 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2510 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 2511 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2512 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 2513 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2514 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 2515 u8 flags5; 2516 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2517 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 2518 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2519 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 2520 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2521 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 2522 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2523 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 2524 u8 flags6; 2525 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2526 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 2527 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2528 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 2529 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2530 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 2531 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2532 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 2533 u8 flags7; 2534 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2535 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 2536 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2537 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 2538 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2539 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2540 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2541 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 2542 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2543 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 2544 u8 flags8; 2545 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2546 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 2547 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2548 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 2549 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 2550 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 2551 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2552 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2553 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 2554 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 2555 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2556 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2557 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2558 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 2559 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2560 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 2561 u8 flags9; 2562 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2563 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 2564 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2565 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 2566 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2567 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 2568 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2569 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 2570 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2571 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 2572 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2573 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 2574 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2575 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 2576 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2577 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 2578 u8 flags10; 2579 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2580 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 2581 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2582 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 2583 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2584 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 2585 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2586 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 2587 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2588 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2589 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2590 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 2591 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2592 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 2593 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2594 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 2595 u8 flags11; 2596 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2597 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 2598 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2599 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 2600 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2601 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 2602 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2603 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 2604 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2605 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 2606 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2607 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 2608 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2609 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2610 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2611 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 2612 u8 flags12; 2613 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2614 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 2615 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule11en */ 2616 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 2617 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2618 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2619 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2620 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2621 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2622 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 2623 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2624 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 2625 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2626 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 2627 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2628 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 2629 u8 flags13; 2630 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2631 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 2632 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2633 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 2634 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2635 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2636 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2637 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2638 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2639 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2640 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2641 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2642 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2643 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2644 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2645 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2646 u8 flags14; 2647 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 2648 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 2649 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2650 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 2651 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 2652 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 2653 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 2654 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 2655 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 2656 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 2657 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 2658 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 2659 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2660 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 2661 u8 byte2 /* byte2 */; 2662 __le16 physical_q0 /* physical_q0 */; 2663 __le16 word1 /* physical_q1 */; 2664 __le16 irq_prod /* physical_q2 */; 2665 __le16 word3 /* word3 */; 2666 __le16 word4 /* word4 */; 2667 __le16 ack_cons /* word5 */; 2668 __le16 irq_cons /* conn_dpi */; 2669 u8 rxmit_opcode /* byte3 */; 2670 u8 byte4 /* byte4 */; 2671 u8 byte5 /* byte5 */; 2672 u8 byte6 /* byte6 */; 2673 __le32 rxmit_psn_and_id /* reg0 */; 2674 __le32 rxmit_bytes_length /* reg1 */; 2675 __le32 psn /* reg2 */; 2676 __le32 reg3 /* reg3 */; 2677 __le32 reg4 /* reg4 */; 2678 __le32 reg5 /* cf_array0 */; 2679 __le32 msn_and_syndrome /* cf_array1 */; 2680 }; 2681 2682 struct e5_ystorm_roce_req_conn_ag_ctx 2683 { 2684 u8 byte0 /* cdu_validation */; 2685 u8 byte1 /* state_and_core_id */; 2686 u8 flags0; 2687 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2688 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2689 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2690 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2691 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2692 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2693 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2694 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2695 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2696 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2697 u8 flags1; 2698 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2699 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2700 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2701 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2702 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2703 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2704 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2705 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 2706 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2707 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 2708 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2709 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 2710 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2711 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 2712 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2713 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 2714 u8 byte2 /* byte2 */; 2715 u8 byte3 /* byte3 */; 2716 __le16 word0 /* word0 */; 2717 __le32 reg0 /* reg0 */; 2718 __le32 reg1 /* reg1 */; 2719 __le16 word1 /* word1 */; 2720 __le16 word2 /* word2 */; 2721 __le16 word3 /* word3 */; 2722 __le16 word4 /* word4 */; 2723 __le32 reg2 /* reg2 */; 2724 __le32 reg3 /* reg3 */; 2725 }; 2726 2727 struct e5_ystorm_roce_resp_conn_ag_ctx 2728 { 2729 u8 byte0 /* cdu_validation */; 2730 u8 byte1 /* state_and_core_id */; 2731 u8 flags0; 2732 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2733 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2734 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2735 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2736 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2737 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2738 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2739 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2740 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2741 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2742 u8 flags1; 2743 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2744 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2745 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2746 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2747 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2748 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2749 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2750 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 2751 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2752 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 2753 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2754 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 2755 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2756 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 2757 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2758 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 2759 u8 byte2 /* byte2 */; 2760 u8 byte3 /* byte3 */; 2761 __le16 word0 /* word0 */; 2762 __le32 reg0 /* reg0 */; 2763 __le32 reg1 /* reg1 */; 2764 __le16 word1 /* word1 */; 2765 __le16 word2 /* word2 */; 2766 __le16 word3 /* word3 */; 2767 __le16 word4 /* word4 */; 2768 __le32 reg2 /* reg2 */; 2769 __le32 reg3 /* reg3 */; 2770 }; 2771 2772 /* 2773 * Roce doorbell data 2774 */ 2775 enum roce_flavor 2776 { 2777 PLAIN_ROCE /* RoCE v1 */, 2778 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */, 2779 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */, 2780 MAX_ROCE_FLAVOR 2781 }; 2782 2783 #endif /* __ECORE_HSI_ROCE__ */ 2784