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Searched refs:DepReg (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp304 SDep::Kind DepType, unsigned DepReg) { in isCallDependent() argument
306 if (DepReg == HRI->getRARegister()) in isCallDependent()
310 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister()) in isCallDependent()
320 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit()) in isCallDependent()
408 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, in canPromoteToDotCur() argument
446 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo())) in canPromoteToDotCur()
652 const MachineInstr &PacketMI, unsigned DepReg) { in canPromoteToNewValueStore() argument
659 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
681 getPostIncrementOperand(MI, HII).getReg() == DepReg) { in canPromoteToNewValueStore()
686 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) { in canPromoteToNewValueStore()
[all …]
H A DHexagonVLIWPacketizer.h120 unsigned DepReg);
125 unsigned DepReg, MachineBasicBlock::iterator &MII,
133 unsigned DepReg, MachineBasicBlock::iterator &MII,
136 unsigned DepReg, MachineBasicBlock::iterator &MII);
138 const MachineInstr &PacketMI, unsigned DepReg);