1//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for AArch64 architecture. 10// 11//===----------------------------------------------------------------------===// 12 13/// CCIfBigEndian - Match only if we're in big endian mode. 14class CCIfBigEndian<CCAction A> : 15 CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>; 16 17class CCIfILP32<CCAction A> : 18 CCIf<"State.getMachineFunction().getDataLayout().getPointerSize() == 4", A>; 19 20/// CCIfSubtarget - Match if the current subtarget has a feature F. 21class CCIfSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("State.getMachineFunction()" 23 ".getSubtarget<AArch64Subtarget>().", F), 24 A>; 25 26//===----------------------------------------------------------------------===// 27// ARM AAPCS64 Calling Convention 28//===----------------------------------------------------------------------===// 29 30defvar AArch64_Common = [ 31 CCIfType<[iPTR], CCBitConvertToType<i64>>, 32 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 33 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 34 35 // Big endian vectors must be passed as if they were 1-element vectors so that 36 // their lanes are in a consistent order. 37 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 38 CCBitConvertToType<f64>>>, 39 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 40 CCBitConvertToType<f128>>>, 41 42 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter. 43 // However, on windows, in some circumstances, the SRet is passed in X0 or X1 44 // instead. The presence of the inreg attribute indicates that SRet is 45 // passed in the alternative register (X0 or X1), not X8: 46 // - X0 for non-instance methods. 47 // - X1 for instance methods. 48 49 // The "sret" attribute identifies indirect returns. 50 // The "inreg" attribute identifies non-aggregate types. 51 // The position of the "sret" attribute identifies instance/non-instance 52 // methods. 53 // "sret" on argument 0 means non-instance methods. 54 // "sret" on argument 1 means instance methods. 55 56 CCIfInReg<CCIfType<[i64], 57 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>, 58 59 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>, 60 61 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 62 // slot is 64-bit. 63 CCIfByVal<CCPassByVal<8, 8>>, 64 65 // Pass SwiftSelf in a callee saved register. 66 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>, 67 68 // A SwiftError is passed in X21. 69 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>, 70 71 // Pass SwiftAsync in an otherwise callee saved register so that it will be 72 // preserved for normal function calls. 73 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X22]>>>, 74 75 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 76 77 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 78 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 79 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 80 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 81 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 82 CCPassIndirect<i64>>, 83 84 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount], 85 CCAssignToReg<[P0, P1, P2, P3]>>, 86 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount], 87 CCPassIndirect<i64>>, 88 89 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 90 // up to eight each of GPR and FPR. 91 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 92 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>, 93 // i128 is split to two i64s, we can't fit half to register X7. 94 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6], 95 [X0, X1, X3, X5]>>>, 96 97 // i128 is split to two i64s, and its stack alignment is 16 bytes. 98 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 99 100 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>, 101 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 102 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 103 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>, 104 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 105 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 106 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 107 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 108 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 109 110 // If more than will fit in registers, pass them on the stack instead. 111 CCIfType<[i1, i8, i16, f16, bf16], CCAssignToStack<8, 8>>, 112 CCIfType<[i32, f32], CCAssignToStack<8, 8>>, 113 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 114 CCAssignToStack<8, 8>>, 115 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 116 CCAssignToStack<16, 16>> 117]; 118 119let Entry = 1 in 120def CC_AArch64_AAPCS : CallingConv<!listconcat( 121 // The 'nest' parameter, if any, is passed in X18. 122 // Darwin and Windows use X18 as the platform register and hence 'nest' isn't 123 // currently supported there. 124 [CCIfNest<CCAssignToReg<[X18]>>], 125 AArch64_Common 126)>; 127 128let Entry = 1 in 129def RetCC_AArch64_AAPCS : CallingConv<[ 130 CCIfType<[iPTR], CCBitConvertToType<i64>>, 131 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 132 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 133 134 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 135 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>, 136 137 // Big endian vectors must be passed as if they were 1-element vectors so that 138 // their lanes are in a consistent order. 139 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8], 140 CCBitConvertToType<f64>>>, 141 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 142 CCBitConvertToType<f128>>>, 143 144 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 145 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>, 146 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>, 147 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 148 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 149 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>, 150 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 152 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 153 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 154 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 155 156 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 157 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 158 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, 159 160 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount], 161 CCAssignToReg<[P0, P1, P2, P3]>> 162]>; 163 164let Entry = 1 in 165def CC_AArch64_Win64PCS : CallingConv<AArch64_Common>; 166 167// Vararg functions on windows pass floats in integer registers 168let Entry = 1 in 169def CC_AArch64_Win64_VarArg : CallingConv<[ 170 CCIfType<[f16, bf16], CCBitConvertToType<i16>>, 171 CCIfType<[f32], CCBitConvertToType<i32>>, 172 CCIfType<[f64], CCBitConvertToType<i64>>, 173 CCDelegateTo<CC_AArch64_Win64PCS> 174]>; 175 176// Vararg functions on Arm64EC ABI use a different convention, using 177// a stack layout compatible with the x64 calling convention. 178let Entry = 1 in 179def CC_AArch64_Arm64EC_VarArg : CallingConv<[ 180 // Convert small floating-point values to integer. 181 CCIfType<[f16, bf16], CCBitConvertToType<i16>>, 182 CCIfType<[f32], CCBitConvertToType<i32>>, 183 CCIfType<[f64, v1f64, v1i64, v2f32, v2i32, v4i16, v4f16, v4bf16, v8i8, iPTR], 184 CCBitConvertToType<i64>>, 185 186 // Larger floating-point/vector values are passed indirectly. 187 CCIfType<[f128, v2f64, v2i64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8], 188 CCPassIndirect<i64>>, 189 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, 190 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64], 191 CCPassIndirect<i64>>, 192 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], 193 CCPassIndirect<i64>>, 194 195 // Handle SRet. See comment in CC_AArch64_AAPCS. 196 CCIfInReg<CCIfType<[i64], 197 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>, 198 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>, 199 200 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 201 // slot is 64-bit. (Shouldn't normally come up; the Microsoft ABI doesn't 202 // use byval.) 203 CCIfByVal<CCPassByVal<8, 8>>, 204 205 // Promote small integers to i32 206 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 207 208 // Pass first four arguments in x0-x3. 209 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3]>>, 210 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3]>>, 211 212 // Put remaining arguments on stack. 213 CCIfType<[i32, i64], CCAssignToStack<8, 8>>, 214]>; 215 216// Arm64EC thunks use a calling convention that's precisely the x64 calling 217// convention, except that the registers have different names, and the callee 218// address is passed in X9. 219let Entry = 1 in 220def CC_AArch64_Arm64EC_Thunk : CallingConv<[ 221 // ARM64EC-specific: the InReg attribute can be used to access the x64 sp passed into entry thunks in x4 from the IR. 222 CCIfInReg<CCIfType<[i64], CCAssignToReg<[X4]>>>, 223 224 // Byval aggregates are passed by pointer 225 CCIfByVal<CCPassIndirect<i64>>, 226 227 // ARM64EC-specific: promote small integers to i32. (x86 only promotes i1, 228 // but that would confuse ARM64 lowering code.) 229 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 230 231 // The 'nest' parameter, if any, is passed in R10 (X4). 232 CCIfNest<CCAssignToReg<[X4]>>, 233 234 // A SwiftError is passed in R12 (X19). 235 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X19]>>>, 236 237 // Pass SwiftSelf in R13 (X20). 238 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>, 239 240 // Pass SwiftAsync in an otherwise callee saved register so that calls to 241 // normal functions don't need to save it somewhere. 242 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X21]>>>, 243 244 // The 'CFGuardTarget' parameter, if any, is passed in RAX (R8). 245 CCIfCFGuardTarget<CCAssignToReg<[X8]>>, 246 247 // 128 bit vectors are passed by pointer 248 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>, 249 250 // 256 bit vectors are passed by pointer 251 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>, 252 253 // 512 bit vectors are passed by pointer 254 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 255 256 // Long doubles are passed by pointer 257 CCIfType<[f80], CCPassIndirect<i64>>, 258 259 // The first 4 MMX vector arguments are passed in GPRs. 260 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 261 262 // The first 4 FP/Vector arguments are passed in XMM registers. 263 CCIfType<[f16], 264 CCAssignToRegWithShadow<[H0, H1, H2, H3], 265 [X0, X1, X2, X3]>>, 266 CCIfType<[f32], 267 CCAssignToRegWithShadow<[S0, S1, S2, S3], 268 [X0, X1, X2, X3]>>, 269 CCIfType<[f64], 270 CCAssignToRegWithShadow<[D0, D1, D2, D3], 271 [X0, X1, X2, X3]>>, 272 273 // The first 4 integer arguments are passed in integer registers. 274 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3], 275 [Q0, Q1, Q2, Q3]>>, 276 277 // Arm64EC thunks: the first argument is always a pointer to the destination 278 // address, stored in x9. 279 CCIfType<[i64], CCAssignToReg<[X9]>>, 280 281 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3], 282 [Q0, Q1, Q2, Q3]>>, 283 284 // Integer/FP values get stored in stack slots that are 8 bytes in size and 285 // 8-byte aligned if there are no more registers to hold them. 286 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>> 287]>; 288 289// The native side of ARM64EC thunks 290let Entry = 1 in 291def CC_AArch64_Arm64EC_Thunk_Native : CallingConv<[ 292 CCIfType<[i64], CCAssignToReg<[X9]>>, 293 CCDelegateTo<CC_AArch64_AAPCS> 294]>; 295 296let Entry = 1 in 297def RetCC_AArch64_Arm64EC_Thunk : CallingConv<[ 298 // The X86-Win64 calling convention always returns __m64 values in RAX. 299 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 300 301 // Otherwise, everything is the same as 'normal' X86-64 C CC. 302 303 // The X86-64 calling convention always returns FP values in XMM0. 304 CCIfType<[f16], CCAssignToReg<[H0, H1]>>, 305 CCIfType<[f32], CCAssignToReg<[S0, S1]>>, 306 CCIfType<[f64], CCAssignToReg<[D0, D1]>>, 307 CCIfType<[f128], CCAssignToReg<[Q0, Q1]>>, 308 309 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X19]>>>, 310 311 // Scalar values are returned in AX first, then DX. For i8, the ABI 312 // requires the values to be in AL and AH, however this code uses AL and DL 313 // instead. This is because using AH for the second register conflicts with 314 // the way LLVM does multiple return values -- a return of {i16,i8} would end 315 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 316 // for functions that return two i8 values are currently expected to pack the 317 // values into an i16 (which uses AX, and thus AL:AH). 318 // 319 // For code that doesn't care about the ABI, we allow returning more than two 320 // integer values in registers. 321 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 322 CCIfType<[i32], CCAssignToReg<[W8, W1, W0]>>, 323 CCIfType<[i64], CCAssignToReg<[X8, X1, X0]>>, 324 325 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 326 // can only be used by ABI non-compliant code. If the target doesn't have XMM 327 // registers, it won't have vector types. 328 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 329 CCAssignToReg<[Q0, Q1, Q2, Q3]>> 330]>; 331 332// Windows Control Flow Guard checks take a single argument (the target function 333// address) and have no return value. 334let Entry = 1 in 335def CC_AArch64_Win64_CFGuard_Check : CallingConv<[ 336 CCIfType<[i64], CCAssignToReg<[X15]>> 337]>; 338 339let Entry = 1 in 340def CC_AArch64_Arm64EC_CFGuard_Check : CallingConv<[ 341 CCIfType<[i64], CCAssignToReg<[X11, X10, X9]>> 342]>; 343 344let Entry = 1 in 345def RetCC_AArch64_Arm64EC_CFGuard_Check : CallingConv<[ 346 CCIfType<[i64], CCAssignToReg<[X11]>> 347]>; 348 349 350// Darwin uses a calling convention which differs in only two ways 351// from the standard one at this level: 352// + i128s (i.e. split i64s) don't need even registers. 353// + Stack slots are sized as needed rather than being at least 64-bit. 354let Entry = 1 in 355def CC_AArch64_DarwinPCS : CallingConv<[ 356 CCIfType<[iPTR], CCBitConvertToType<i64>>, 357 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 358 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 359 360 // An SRet is passed in X8, not X0 like a normal pointer parameter. 361 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>, 362 363 // Put ByVal arguments directly on the stack. Minimum size and alignment of a 364 // slot is 64-bit. 365 CCIfByVal<CCPassByVal<8, 8>>, 366 367 // Pass SwiftSelf in a callee saved register. 368 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>, 369 370 // A SwiftError is passed in X21. 371 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>, 372 373 // Pass SwiftAsync in an otherwise callee saved register so that it will be 374 // preserved for normal function calls. 375 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X22]>>>, 376 377 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>, 378 379 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 380 // up to eight each of GPR and FPR. 381 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 382 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>, 383 // i128 is split to two i64s, we can't fit half to register X7. 384 CCIfType<[i64], 385 CCIfSplit<CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6]>>>, 386 // i128 is split to two i64s, and its stack alignment is 16 bytes. 387 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>, 388 389 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>, 390 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 391 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>, 392 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>, 393 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 394 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 395 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 396 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 397 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 398 399 // If more than will fit in registers, pass them on the stack instead. 400 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>, 401 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16", 402 CCAssignToStack<2, 2>>, 403 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 404 405 // Re-demote pointers to 32-bits so we don't end up storing 64-bit 406 // values and clobbering neighbouring stack locations. Not very pretty. 407 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 408 CCIfPtr<CCIfILP32<CCAssignToStack<4, 4>>>, 409 410 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16], 411 CCAssignToStack<8, 8>>, 412 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 413 CCAssignToStack<16, 16>> 414]>; 415 416let Entry = 1 in 417def CC_AArch64_DarwinPCS_VarArg : CallingConv<[ 418 CCIfType<[iPTR], CCBitConvertToType<i64>>, 419 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 420 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 421 422 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Stack_Block">>, 423 424 // Handle all scalar types as either i64 or f64. 425 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 426 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>, 427 428 // Everything is on the stack. 429 // i128 is split to two i64s, and its stack alignment is 16 bytes. 430 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 431 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 432 CCAssignToStack<8, 8>>, 433 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 434 CCAssignToStack<16, 16>> 435]>; 436 437// In the ILP32 world, the minimum stack slot size is 4 bytes. Otherwise the 438// same as the normal Darwin VarArgs handling. 439let Entry = 1 in 440def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[ 441 CCIfType<[v2f32], CCBitConvertToType<v2i32>>, 442 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 443 444 // Handle all scalar types as either i32 or f32. 445 CCIfType<[i8, i16], CCPromoteToType<i32>>, 446 CCIfType<[f16, bf16], CCPromoteToType<f32>>, 447 448 // Everything is on the stack. 449 // i128 is split to two i64s, and its stack alignment is 16 bytes. 450 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>, 451 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 452 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>, 453 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16], 454 CCAssignToStack<8, 8>>, 455 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16], 456 CCAssignToStack<16, 16>> 457]>; 458 459//===----------------------------------------------------------------------===// 460// ARM64 Calling Convention for GHC 461//===----------------------------------------------------------------------===// 462 463// This calling convention is specific to the Glasgow Haskell Compiler. 464// The only documentation is the GHC source code, specifically the C header 465// file: 466// 467// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs.h 468// 469// which defines the registers for the Spineless Tagless G-Machine (STG) that 470// GHC uses to implement lazy evaluation. The generic STG machine has a set of 471// registers which are mapped to appropriate set of architecture specific 472// registers for each CPU architecture. 473// 474// The STG Machine is documented here: 475// 476// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode 477// 478// The AArch64 register mapping is defined in the following header file: 479// 480// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm64.h 481// 482 483let Entry = 1 in 484def CC_AArch64_GHC : CallingConv<[ 485 CCIfType<[iPTR], CCBitConvertToType<i64>>, 486 487 // Handle all vector types as either f64 or v2f64. 488 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 489 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>, 490 491 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 492 CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>, 493 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>, 494 495 // Promote i8/i16/i32 arguments to i64. 496 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 497 498 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 499 CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>> 500]>; 501 502let Entry = 1 in 503def CC_AArch64_Preserve_None : CallingConv<[ 504 // VarArgs are only supported using the C calling convention. 505 // This handles the non-variadic parameter case. Variadic parameters 506 // are handled in CCAssignFnForCall. 507 CCIfVarArg<CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_AArch64_DarwinPCS>>>, 508 CCIfVarArg<CCIfSubtarget<"isTargetWindows()", CCDelegateTo<CC_AArch64_Win64PCS>>>, 509 CCIfVarArg<CCDelegateTo<CC_AArch64_AAPCS>>, 510 511 // We can pass arguments in all general registers, except: 512 // - X8, used for sret 513 // - X16/X17, used by the linker as IP0/IP1 514 // - X18, the platform register 515 // - X19, the base pointer 516 // - X29, the frame pointer 517 // - X30, the link register 518 // General registers are not preserved with the exception of 519 // FP, LR, and X18 520 // Non-volatile registers are used first, so functions may call 521 // normal functions without saving and reloading arguments. 522 // X9 is assigned last as it is used in FrameLowering as the first 523 // choice for a scratch register. 524 CCIfType<[i32], CCAssignToReg<[W20, W21, W22, W23, 525 W24, W25, W26, W27, W28, 526 W0, W1, W2, W3, W4, W5, 527 W6, W7, W10, W11, 528 W12, W13, W14, W9]>>, 529 CCIfType<[i64], CCAssignToReg<[X20, X21, X22, X23, 530 X24, X25, X26, X27, X28, 531 X0, X1, X2, X3, X4, X5, 532 X6, X7, X10, X11, 533 X12, X13, X14, X9]>>, 534 535 // Windows uses X15 for stack allocation 536 CCIf<"!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()", 537 CCIfType<[i32], CCAssignToReg<[W15]>>>, 538 CCIf<"!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()", 539 CCIfType<[i64], CCAssignToReg<[X15]>>>, 540 541 CCDelegateTo<CC_AArch64_AAPCS> 542]>; 543 544// The order of the callee-saves in this file is important, because the 545// FrameLowering code will use this order to determine the layout the 546// callee-save area in the stack frame. As can be observed below, Darwin 547// requires the frame-record (LR, FP) to be at the top the callee-save area, 548// whereas for other platforms they are at the bottom. 549 550// FIXME: LR is only callee-saved in the sense that *we* preserve it and are 551// presumably a callee to someone. External functions may not do so, but this 552// is currently safe since BL has LR as an implicit-def and what happens after a 553// tail call doesn't matter. 554// 555// It would be better to model its preservation semantics properly (create a 556// vreg on entry, use it in RET & tail call generation; make that vreg def if we 557// end up saving LR as part of a call frame). Watch this space... 558def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 559 X25, X26, X27, X28, LR, FP, 560 D8, D9, D10, D11, 561 D12, D13, D14, D15)>; 562 563// A variant for treating X18 as callee saved, when interfacing with 564// code that needs X18 to be preserved. 565def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>; 566 567// Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x. 568// We put FP before LR, so that frame lowering logic generates (FP,LR) pairs, 569// and not (LR,FP) pairs. 570def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 571 X25, X26, X27, X28, FP, LR, 572 D8, D9, D10, D11, 573 D12, D13, D14, D15)>; 574 575def CSR_Win_AArch64_AAPCS_SwiftError 576 : CalleeSavedRegs<(sub CSR_Win_AArch64_AAPCS, X21)>; 577 578def CSR_Win_AArch64_AAPCS_SwiftTail 579 : CalleeSavedRegs<(sub CSR_Win_AArch64_AAPCS, X20, X22)>; 580 581// The Control Flow Guard check call uses a custom calling convention that also 582// preserves X0-X8 and Q0-Q7. 583def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS, 584 (sequence "X%u", 0, 8), 585 (sequence "Q%u", 0, 7))>; 586 587// To match the x64 calling convention, Arm64EC thunks preserve q6-q15. 588def CSR_Win_AArch64_Arm64EC_Thunk : CalleeSavedRegs<(add (sequence "Q%u", 6, 15), 589 X19, X20, X21, X22, X23, X24, 590 X25, X26, X27, X28, FP, LR)>; 591 592// AArch64 PCS for vector functions (VPCS) 593// must (additionally) preserve full Q8-Q23 registers 594def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, 595 X25, X26, X27, X28, LR, FP, 596 (sequence "Q%u", 8, 23))>; 597 598// Functions taking SVE arguments or returning an SVE type 599// must (additionally) preserve full Z8-Z23 and predicate registers P4-P15 600def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23), 601 (sequence "P%u", 4, 15), 602 X19, X20, X21, X22, X23, X24, 603 X25, X26, X27, X28, LR, FP)>; 604 605// SME ABI support routines such as __arm_tpidr2_save/restore preserve most registers. 606def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0 607 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31), 608 (sequence "P%u", 0, 15), 609 (sequence "X%u", 0, 13), 610 (sequence "X%u",19, 28), 611 LR, FP)>; 612 613// SME ABI support routines such as __arm_get_current_vg preserve most registers. 614def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1 615 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31), 616 (sequence "P%u", 0, 15), 617 (sequence "X%u", 1, 15), 618 (sequence "X%u",19, 28), 619 LR, FP)>; 620 621// SME ABI support routines __arm_sme_state preserves most registers. 622def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2 623 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31), 624 (sequence "P%u", 0, 15), 625 (sequence "X%u", 2, 15), 626 (sequence "X%u",19, 28), 627 LR, FP)>; 628 629// The SMSTART/SMSTOP instructions preserve only GPR registers. 630def CSR_AArch64_SMStartStop : CalleeSavedRegs<(add (sequence "X%u", 0, 28), 631 LR, FP)>; 632 633def CSR_AArch64_AAPCS_SwiftTail 634 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X20, X22)>; 635 636// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since 637// 'this' and the pointer return value are both passed in X0 in these cases, 638// this can be partially modelled by treating X0 as a callee-saved register; 639// only the resulting RegMask is used; the SaveList is ignored 640// 641// (For generic ARM 64-bit ABI code, clang will not generate constructors or 642// destructors with 'this' returns, so this RegMask will not be used in that 643// case) 644def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>; 645 646def CSR_AArch64_AAPCS_SwiftError 647 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>; 648 649// The ELF stub used for TLS-descriptor access saves every feasible 650// register. Only X0 and LR are clobbered. 651def CSR_AArch64_TLS_ELF 652 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP, 653 (sequence "Q%u", 0, 31))>; 654 655def CSR_AArch64_AllRegs 656 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP, 657 (sequence "X%u", 0, 28), FP, LR, SP, 658 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31), 659 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31), 660 (sequence "Q%u", 0, 31))>; 661 662def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>; 663 664def CSR_AArch64_NoneRegs : CalleeSavedRegs<(add LR, FP)>; 665 666def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS, 667 (sequence "X%u", 9, 15))>; 668 669def CSR_AArch64_RT_AllRegs : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, 670 (sequence "Q%u", 8, 31))>; 671 672def CSR_AArch64_StackProbe_Windows 673 : CalleeSavedRegs<(add (sequence "X%u", 0, 15), 674 (sequence "X%u", 18, 28), FP, SP, 675 (sequence "Q%u", 0, 31))>; 676 677// Darwin variants of AAPCS. 678// Darwin puts the frame-record at the top of the callee-save area. 679def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22, 680 X23, X24, X25, X26, X27, X28, 681 D8, D9, D10, D11, 682 D12, D13, D14, D15)>; 683 684def CSR_Darwin_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, 685 X22, X23, X24, X25, X26, X27, 686 X28, (sequence "Q%u", 8, 23))>; 687 688// For Windows calling convention on a non-windows OS, where X18 is treated 689// as reserved, back up X18 when entering non-windows code (marked with the 690// Windows calling convention) and restore when returning regardless of 691// whether the individual function uses it - it might call other functions 692// that clobber it. 693def CSR_Darwin_AArch64_AAPCS_Win64 694 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X18)>; 695 696def CSR_Darwin_AArch64_AAPCS_ThisReturn 697 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X0)>; 698 699def CSR_Darwin_AArch64_AAPCS_SwiftError 700 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X21)>; 701 702def CSR_Darwin_AArch64_AAPCS_SwiftTail 703 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X20, X22)>; 704 705// The function used by Darwin to obtain the address of a thread-local variable 706// guarantees more than a normal AAPCS function. x16 and x17 are used on the 707// fast path for calculation, but other registers except X0 (argument/return) 708// and LR (it is a call, after all) are preserved. 709def CSR_Darwin_AArch64_TLS 710 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17), 711 FP, 712 (sequence "Q%u", 0, 31))>; 713 714// We can only handle a register pair with adjacent registers, the register pair 715// should belong to the same class as well. Since the access function on the 716// fast path calls a function that follows CSR_Darwin_AArch64_TLS, 717// CSR_Darwin_AArch64_CXX_TLS should be a subset of CSR_Darwin_AArch64_TLS. 718def CSR_Darwin_AArch64_CXX_TLS 719 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, 720 (sub (sequence "X%u", 1, 28), X9, X15, X16, X17, X18, X19), 721 (sequence "D%u", 0, 31))>; 722 723// CSRs that are handled by prologue, epilogue. 724def CSR_Darwin_AArch64_CXX_TLS_PE 725 : CalleeSavedRegs<(add LR, FP)>; 726 727// CSRs that are handled explicitly via copies. 728def CSR_Darwin_AArch64_CXX_TLS_ViaCopy 729 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_CXX_TLS, LR, FP)>; 730 731def CSR_Darwin_AArch64_RT_MostRegs 732 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, (sequence "X%u", 9, 15))>; 733 734def CSR_Darwin_AArch64_RT_AllRegs 735 : CalleeSavedRegs<(add CSR_Darwin_AArch64_RT_MostRegs, (sequence "Q%u", 8, 31))>; 736 737// Variants of the standard calling conventions for shadow call stack. 738// These all preserve x18 in addition to any other registers. 739def CSR_AArch64_NoRegs_SCS 740 : CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>; 741def CSR_AArch64_NoneRegs_SCS 742 : CalleeSavedRegs<(add CSR_AArch64_NoneRegs, X18)>; 743def CSR_AArch64_AllRegs_SCS 744 : CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>; 745def CSR_AArch64_AAPCS_SwiftError_SCS 746 : CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>; 747def CSR_AArch64_RT_MostRegs_SCS 748 : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>; 749def CSR_AArch64_RT_AllRegs_SCS 750 : CalleeSavedRegs<(add CSR_AArch64_RT_AllRegs, X18)>; 751def CSR_AArch64_AAVPCS_SCS 752 : CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>; 753def CSR_AArch64_SVE_AAPCS_SCS 754 : CalleeSavedRegs<(add CSR_AArch64_SVE_AAPCS, X18)>; 755def CSR_AArch64_AAPCS_SCS 756 : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>; 757