1[ 2 { 3 "Unit": "CBO", 4 "EventCode": "0x22", 5 "UMask": "0x41", 6 "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", 7 "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", 8 "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", 9 "Counter": "0,1", 10 "CounterMask": "0", 11 "Invert": "0", 12 "EdgeDetect": "0" 13 }, 14 { 15 "Unit": "CBO", 16 "EventCode": "0x22", 17 "UMask": "0x81", 18 "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", 19 "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", 20 "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", 21 "Counter": "0,1", 22 "CounterMask": "0", 23 "Invert": "0", 24 "EdgeDetect": "0" 25 }, 26 { 27 "Unit": "CBO", 28 "EventCode": "0x22", 29 "UMask": "0x44", 30 "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", 31 "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", 32 "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", 33 "Counter": "0,1", 34 "CounterMask": "0", 35 "Invert": "0", 36 "EdgeDetect": "0" 37 }, 38 { 39 "Unit": "CBO", 40 "EventCode": "0x22", 41 "UMask": "0x48", 42 "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", 43 "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", 44 "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", 45 "Counter": "0,1", 46 "CounterMask": "0", 47 "Invert": "0", 48 "EdgeDetect": "0" 49 }, 50 { 51 "Unit": "CBO", 52 "EventCode": "0x34", 53 "UMask": "0x21", 54 "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", 55 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", 56 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", 57 "Counter": "0,1", 58 "CounterMask": "0", 59 "Invert": "0", 60 "EdgeDetect": "0" 61 }, 62 { 63 "Unit": "CBO", 64 "EventCode": "0x34", 65 "UMask": "0x81", 66 "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", 67 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 68 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 69 "Counter": "0,1", 70 "CounterMask": "0", 71 "Invert": "0", 72 "EdgeDetect": "0" 73 }, 74 { 75 "Unit": "CBO", 76 "EventCode": "0x34", 77 "UMask": "0x18", 78 "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", 79 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state", 80 "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", 81 "Counter": "0,1", 82 "CounterMask": "0", 83 "Invert": "0", 84 "EdgeDetect": "0" 85 }, 86 { 87 "Unit": "CBO", 88 "EventCode": "0x34", 89 "UMask": "0x88", 90 "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", 91 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 92 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 93 "Counter": "0,1", 94 "CounterMask": "0", 95 "Invert": "0", 96 "EdgeDetect": "0" 97 }, 98 { 99 "Unit": "CBO", 100 "EventCode": "0x34", 101 "UMask": "0x1f", 102 "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", 103 "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state", 104 "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", 105 "Counter": "0,1", 106 "CounterMask": "0", 107 "Invert": "0", 108 "EdgeDetect": "0" 109 }, 110 { 111 "Unit": "CBO", 112 "EventCode": "0x34", 113 "UMask": "0x2f", 114 "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", 115 "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state", 116 "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", 117 "Counter": "0,1", 118 "CounterMask": "0", 119 "Invert": "0", 120 "EdgeDetect": "0" 121 }, 122 { 123 "Unit": "CBO", 124 "EventCode": "0x34", 125 "UMask": "0x8f", 126 "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", 127 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 128 "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 129 "Counter": "0,1", 130 "CounterMask": "0", 131 "Invert": "0", 132 "EdgeDetect": "0" 133 }, 134 { 135 "Unit": "CBO", 136 "EventCode": "0x34", 137 "UMask": "0x86", 138 "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", 139 "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 140 "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 141 "Counter": "0,1", 142 "CounterMask": "0", 143 "Invert": "0", 144 "EdgeDetect": "0" 145 }, 146 { 147 "Unit": "CBO", 148 "EventCode": "0x34", 149 "UMask": "0x16", 150 "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", 151 "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 152 "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 153 "Counter": "0,1", 154 "CounterMask": "0", 155 "Invert": "0", 156 "EdgeDetect": "0" 157 }, 158 { 159 "Unit": "CBO", 160 "EventCode": "0x34", 161 "UMask": "0x26", 162 "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", 163 "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state", 164 "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", 165 "Counter": "0,1", 166 "CounterMask": "0", 167 "Invert": "0", 168 "EdgeDetect": "0" 169 }, 170 { 171 "Unit": "NCU", 172 "EventCode": "0x0", 173 "UMask": "0x01", 174 "EventName": "UNC_CLOCK.SOCKET", 175 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", 176 "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", 177 "Counter": "FIXED", 178 "CounterMask": "0", 179 "Invert": "0", 180 "EdgeDetect": "0" 181 }, 182 { 183 "Unit": "iMPH-U", 184 "EventCode": "0x80", 185 "UMask": "0x01", 186 "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 187 "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.", 188 "PublicDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.", 189 "Counter": "0", 190 "CounterMask": "0", 191 "Invert": "0", 192 "EdgeDetect": "0" 193 }, 194 { 195 "Unit": "iMPH-U", 196 "EventCode": "0x81", 197 "UMask": "0x01", 198 "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 199 "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", 200 "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", 201 "Counter": "0,1", 202 "CounterMask": "0", 203 "Invert": "0", 204 "EdgeDetect": "0" 205 }, 206 { 207 "Unit": "iMPH-U", 208 "EventCode": "0x81", 209 "UMask": "0x02", 210 "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", 211 "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", 212 "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", 213 "Counter": "0,1", 214 "CounterMask": "0", 215 "Invert": "0", 216 "EdgeDetect": "0" 217 }, 218 { 219 "Unit": "iMPH-U", 220 "EventCode": "0x81", 221 "UMask": "0x20", 222 "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", 223 "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", 224 "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", 225 "Counter": "0,1", 226 "CounterMask": "0", 227 "Invert": "0", 228 "EdgeDetect": "0" 229 }, 230 { 231 "Unit": "iMPH-U", 232 "EventCode": "0x84", 233 "UMask": "0x01", 234 "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 235 "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", 236 "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", 237 "Counter": "0,1", 238 "CounterMask": "0", 239 "Invert": "0", 240 "EdgeDetect": "0" 241 }, 242 { 243 "Unit": "iMPH-U", 244 "EventCode": "0x80", 245 "UMask": "0x01", 246 "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", 247 "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 248 "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", 249 "Counter": "0", 250 "CounterMask": "1", 251 "Invert": "0", 252 "EdgeDetect": "0" 253 }, 254 { 255 "Unit": "iMPH-U", 256 "EventCode": "0x80", 257 "UMask": "0x02", 258 "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", 259 "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.", 260 "PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.", 261 "Counter": "0", 262 "CounterMask": "0", 263 "Invert": "0", 264 "EdgeDetect": "0" 265 }, 266 { 267 "Unit": "iMPH-U", 268 "EventCode": "0x81", 269 "UMask": "0x02", 270 "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", 271 "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", 272 "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", 273 "Counter": "0,1", 274 "CounterMask": "0", 275 "Invert": "0", 276 "EdgeDetect": "0" 277 } 278]