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Searched refs:bit (Results 201 – 225 of 2701) sorted by relevance

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/linux/fs/affs/
H A Dbitmap.c44 u32 blk, bmap, bit, mask, tmp; in affs_free_block() local
54 bit = blk % sbi->s_bmap_bits; in affs_free_block()
69 mask = 1 << (bit & 31); in affs_free_block()
70 data = (__be32 *)bh->b_data + bit / 32 + 1; in affs_free_block()
122 u32 blk, bmap, bit, mask, mask2, tmp; in affs_alloc_block() local
182 bit = blk % sbi->s_bmap_bits; in affs_alloc_block()
183 data = (__be32 *)bh->b_data + bit / 32 + 1; in affs_alloc_block()
185 mask = ~0UL << (bit & 31); in affs_alloc_block()
206 bit = ffs(tmp & mask) - 1; in affs_alloc_block()
207 blk += bit + sbi->s_reserved; in affs_alloc_block()
[all …]
/linux/net/netlabel/
H A Dnetlabel_kapi.c612 u32 bit; in netlbl_catmap_walk() local
621 bit = offset % NETLBL_CATMAP_MAPSIZE; in netlbl_catmap_walk()
624 bit = 0; in netlbl_catmap_walk()
626 bitmap = iter->bitmap[idx] >> bit; in netlbl_catmap_walk()
632 bit++; in netlbl_catmap_walk()
635 (NETLBL_CATMAP_MAPSIZE * idx) + bit; in netlbl_catmap_walk()
645 bit = 0; in netlbl_catmap_walk()
668 u32 bit; in netlbl_catmap_walkrng() local
678 bit = offset % NETLBL_CATMAP_MAPSIZE; in netlbl_catmap_walkrng()
681 bit = 0; in netlbl_catmap_walkrng()
[all …]
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.c70 u32 bit, u32 width) in owl_read_field() argument
77 return (tmp >> bit) & mask; in owl_read_field()
81 u32 bit, u32 width) in owl_write_field() argument
86 mask = mask << bit; in owl_write_field()
88 owl_update_bits(pctrl->base + reg, mask, (arg << bit)); in owl_write_field()
225 u32 *bit, in owl_pad_pinconf_reg() argument
236 *bit = info->pullctl->shift; in owl_pad_pinconf_reg()
243 *bit = info->st->shift; in owl_pad_pinconf_reg()
261 u32 reg, bit, width, arg; in owl_pin_config_get() local
265 ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width); in owl_pin_config_get()
[all …]
/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Disp_private.h61 const unsigned int bit) in isp_ctrl_getbit() argument
65 return (val & (1UL << bit)) != 0; in isp_ctrl_getbit()
71 const unsigned int bit) in isp_ctrl_setbit() argument
75 isp_ctrl_store(ID, reg, (data | (1UL << bit))); in isp_ctrl_setbit()
82 const unsigned int bit) in isp_ctrl_clearbit() argument
86 isp_ctrl_store(ID, reg, (data & ~(1UL << bit))); in isp_ctrl_clearbit()
H A Dsp_private.h48 const unsigned int bit) in sp_ctrl_getbit() argument
52 return (val & (1UL << bit)) != 0; in sp_ctrl_getbit()
58 const unsigned int bit) in sp_ctrl_setbit() argument
62 sp_ctrl_store(ID, reg, (data | (1UL << bit))); in sp_ctrl_setbit()
69 const unsigned int bit) in sp_ctrl_clearbit() argument
73 sp_ctrl_store(ID, reg, (data & ~(1UL << bit))); in sp_ctrl_clearbit()
/linux/drivers/infiniband/hw/qib/
H A Dqib_twsi.c89 static void scl_out(struct qib_devdata *dd, u8 bit) in scl_out() argument
98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); in scl_out()
104 if (!bit) in scl_out()
121 static void sda_out(struct qib_devdata *dd, u8 bit) in sda_out() argument
128 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); in sda_out()
209 u8 bit; in wr_byte() local
212 bit = (data >> bit_cntr) & 1; in wr_byte()
213 sda_out(dd, bit); in wr_byte()
/linux/Documentation/networking/
H A Doa-tc6-framework.rst64 Each transmit data chunk begins with a 32-bit data header followed by a
70 chunk consists of a data chunk payload ending with a 32-bit data footer.
177 transaction. For TX data chunks, this bit shall be ’1’.
181 SEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an
184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
197 DV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate
201 the setting of the DV bit in the data header.
203 SV (Bit 20) - Start Valid flag. The SPI host shall set this bit when the
205 transmit data chunk payload. Otherwise, this bit shall be
206 zero. This bit is not to be confused with the Start-of-Frame
[all …]
/linux/drivers/rtc/
H A Drtc-meson.c90 static void meson_rtc_send_bit(struct meson_rtc *rtc, unsigned int bit) in meson_rtc_send_bit() argument
93 bit ? RTC_ADDR0_LINE_SDI : 0); in meson_rtc_send_bit()
100 u32 bit = 1 << (nr - 1); in meson_rtc_send_bits() local
102 while (bit) { in meson_rtc_send_bits()
103 meson_rtc_send_bit(rtc, data & bit); in meson_rtc_send_bits()
104 bit >>= 1; in meson_rtc_send_bits()
119 int bit; in meson_rtc_get_data() local
121 for (bit = 0; bit < RTC_DATA_BITS; bit++) { in meson_rtc_get_data()
/linux/arch/sh/boards/mach-landisk/
H A Dpsw.c34 if (sw_value & (1 << psw_info->bit)) { in psw_irq_handler()
63 .bit = 4,
70 .bit = 0,
77 .bit = 2,
84 .bit = 1,
/linux/Documentation/input/devices/
H A Dsentelic.rst34 Bit5 => Y sign bit
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
51 - Set bit 1 in register 0x40 to 1
66 Bit5 => Y sign bit
67 Bit4 => X sign bit
72 Byte 2: X Movement(9-bit 2's complement integers)
73 Byte 3: Y Movement(9-bit 2's complement integers)
97 1. Set bit 2 or 3 in register 0x40 to 1
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dlp872x.txt10 bit[2]: BUCK output voltage control by external DVS pin or register
12 bit[1]: sleep control by external DVS pin or register
14 bit[0]: time step unit(usec). 1 = 25, 0 = 50
17 bit[7:6]: time step unit(usec). 00 = 32, 01 = 64, 10 = 128, 11 = 256
18 bit[4]: BUCK2 enable control. 1 = enable, 0 = disable
19 bit[3]: BUCK2 output voltage register address. 1 = 0Ah, 0 = 0Bh
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
22 bit[1]: LDO sleep control. 1 = sleep mode, 0 = normal
23 bit[0]: BUCK1 enable control, 1 = enable, 0 = disable
/linux/drivers/gpio/
H A Dgpio-bcm-kona.c130 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_set() local
145 val |= BIT(bit); in bcm_kona_gpio_set()
157 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_get() local
176 return !!(val & BIT(bit)); in bcm_kona_gpio_get()
221 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_direction_output() local
236 val |= BIT(bit); in bcm_kona_gpio_direction_output()
336 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_irq_ack() local
345 val |= BIT(bit); in bcm_kona_gpio_irq_ack()
357 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_irq_mask() local
366 val |= BIT(bit); in bcm_kona_gpio_irq_mask()
[all …]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl.h48 #define SPPCTL_SET_MOON_REG_BIT(bit) (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit)) argument
49 #define SPPCTL_CLR_MOON_REG_BIT(bit) BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) argument
/linux/arch/x86/boot/
H A Dpmjump.S41 # Transition to 32-bit mode
50 # Set up data segments for flat 32-bit mode
56 # The 32-bit code sets up its own stack, but this way we do have
64 # 32-bit boot protocol
74 jmpl *%eax # Jump to the 32-bit entrypoint
/linux/drivers/pinctrl/
H A Dpinctrl-cy8c95x0.c704 u8 bit = cypress_get_pin_mask(chip, off); in cy8c95x0_gpio_direction_output() local
708 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); in cy8c95x0_gpio_direction_output()
719 u8 bit = cypress_get_pin_mask(chip, off); in cy8c95x0_gpio_get_value() local
734 return !!(reg_val & bit); in cy8c95x0_gpio_get_value()
742 u8 bit = cypress_get_pin_mask(chip, off); in cy8c95x0_gpio_set_value() local
744 cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); in cy8c95x0_gpio_set_value()
751 u8 bit = cypress_get_pin_mask(chip, off); in cy8c95x0_gpio_get_direction() local
759 if (reg_val & bit) in cy8c95x0_gpio_get_direction()
773 u8 bit = cypress_get_pin_mask(chip, off); in cy8c95x0_gpio_get_pincfg() local
837 if (reg_val & bit) in cy8c95x0_gpio_get_pincfg()
[all …]
/linux/include/linux/soc/qcom/
H A Dsmem_state.h16 struct qcom_smem_state *qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
17 …t qcom_smem_state *devm_qcom_smem_state_get(struct device *dev, const char *con_id, unsigned *bit);
28 const char *con_id, unsigned *bit) in qcom_smem_state_get() argument
35 unsigned *bit) in devm_qcom_smem_state_get() argument
/linux/drivers/clk/pxa/
H A Dclk-pxa27x.c111 bit, is_lp, flags) \ argument
112 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
113 is_lp, CKEN, CKEN_ ## bit, flags)
114 #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ argument
116 div_hp, bit, pxa27x_is_ppll_disabled, 0)
124 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ argument
125 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
126 CKEN, CKEN_ ## bit, 0)
127 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ argument
128 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-generic.rst22 The V4L2_META_FMT_GENERIC_8 format is a plain 8-bit metadata format. This format
26 packed into one 16-bit Data Unit. Otherwise the 16 bits per pixel dataformat is
55 V4L2_META_FMT_GENERIC_CSI2_10 contains 8-bit generic metadata packed in 10-bit
99 V4L2_META_FMT_GENERIC_CSI2_12 contains 8-bit generic metadata packed in 12-bit
145 V4L2_META_FMT_GENERIC_CSI2_14 contains 8-bit generic metadata packed in 14-bit
188 V4L2_META_FMT_GENERIC_CSI2_16 contains 8-bit generic metadata packed in 16-bit
198 16-bit image data. In that case the dataformat is
237 V4L2_META_FMT_GENERIC_CSI2_20 contains 8-bit generic metadata packed in 20-bit
247 16-bit image data. In that case the dataformat is
290 V4L2_META_FMT_GENERIC_CSI2_24 contains 8-bit generic metadata packed in 24-bit
[all …]
/linux/arch/mips/kernel/
H A Dbranch.c146 unsigned int bit; in __mm_isBranchInstr() local
162 bit = (insn.mm_i_format.rs >> 2); in __mm_isBranchInstr()
163 bit += (bit != 0); in __mm_isBranchInstr()
164 bit += 23; in __mm_isBranchInstr()
165 if (fcr31 & (1 << bit)) in __mm_isBranchInstr()
688 unsigned int bit, fcr31, reg; in __compute_return_epc_for_insn() local
696 bit = get_fpr32(&current->thread.fpu.fpr[reg], 0) & 0x1; in __compute_return_epc_for_insn()
698 bit = !bit; in __compute_return_epc_for_insn()
700 if (bit) in __compute_return_epc_for_insn()
717 bit = (insn.i_format.rt >> 2); in __compute_return_epc_for_insn()
[all …]
/linux/tools/perf/util/
H A Dmem2node.c67 u64 bit; in mem2node__init() local
71 for (bit = 0; bit < n->size; bit++) { in mem2node__init()
74 if (!test_bit(bit, n->set)) in mem2node__init()
77 start = bit * bsize; in mem2node__init()
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dinterface.txt30 - ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
38 ti,bit-shift = <3>;
46 ti,bit-shift = <0>;
54 ti,bit-shift = <0>;
H A Ddivider.txt39 Any zero value in this array means the corresponding bit-value is invalid
62 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
71 - ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
73 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
76 - ti,latch-bit : latch the divider value to HW, only needed if the register
94 ti,bit-shift = <24>;
112 ti,bit-shift = <8>;
H A Dfixed-factor-clock.txt18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
21 - ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
41 ti,invert-autoidle-bit;
/linux/arch/powerpc/kernel/
H A Dkprobes-ftrace.c22 int bit; in kprobe_ftrace_handler() local
27 bit = ftrace_test_recursion_trylock(nip, parent_nip); in kprobe_ftrace_handler()
28 if (bit < 0) in kprobe_ftrace_handler()
66 ftrace_test_recursion_unlock(bit); in kprobe_ftrace_handler()
/linux/arch/arm/boot/dts/vt8500/
H A Dwm8750.dtsi159 enable-bit = <24>;
167 enable-bit = <25>;
175 enable-bit = <26>;
183 enable-bit = <27>;
191 enable-bit = <28>;
199 enable-bit = <29>;
208 enable-bit = <17>;
218 enable-bit = <0>;
227 enable-bit = <8>;
236 enable-bit = <9>;

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