Searched hist:"97 ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3" (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/char/agp/ |
| H A D | intel-gtt.c | diff 16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c Tue Nov 02 10:30:46 CET 2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff d110852513148a7ec44fad4e036455aeb816d713 Tue Nov 02 10:30:46 CET 2010 Zhenyu Wang <zhenyuw@linux.intel.com> agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3 Thu Sep 09 17:52:20 CEST 2010 Daniel Vetter <daniel.vetter@ffwll.ch> intel-gtt: introduce pte write function for gen6
Like for i830. intel_i9xx_configure is now unused, so kill it.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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