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/titanic_51/usr/src/uts/common/io/pciex/
H A Dpcieb.hdiff 83e6495b5bcdb3fbe09948670b92d3e265047dcc Fri May 07 04:17:59 CEST 2010 Daniel Ice <Daniel.Ice@Sun.COM> 6896094 For Intel 41210 PCIe2PCI Bridge, MPS for F0 and F2 should be initialized at the same time

H A Dpcie.cdiff 83e6495b5bcdb3fbe09948670b92d3e265047dcc Fri May 07 04:17:59 CEST 2010 Daniel Ice <Daniel.Ice@Sun.COM> 6896094 For Intel 41210 PCIe2PCI Bridge, MPS for F0 and F2 should be initialized at the same time

H A Dpcieb.cdiff 83e6495b5bcdb3fbe09948670b92d3e265047dcc Fri May 07 04:17:59 CEST 2010 Daniel Ice <Daniel.Ice@Sun.COM> 6896094 For Intel 41210 PCIe2PCI Bridge, MPS for F0 and F2 should be initialized at the same time