Searched hist:"8034945 d1a5e56f7eb1885cdd21801f93153b5a6" (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/gpu/drm/i915/ |
| H A D | intel_gvt_mmio_table.c | diff 8034945d1a5e56f7eb1885cdd21801f93153b5a6 Wed Apr 17 17:12:11 CEST 2024 Ville Syrjälä <ville.syrjala@linux.intel.com> drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.
v2: Adjust gvt accordingly
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417151211.32135-1-ville.syrjala@linux.intel.com
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpio_phy.c | diff 8034945d1a5e56f7eb1885cdd21801f93153b5a6 Wed Apr 17 17:12:11 CEST 2024 Ville Syrjälä <ville.syrjala@linux.intel.com> drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.
v2: Adjust gvt accordingly
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417151211.32135-1-ville.syrjala@linux.intel.com
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| H A D | intel_dpll_mgr.c | diff 8034945d1a5e56f7eb1885cdd21801f93153b5a6 Wed Apr 17 17:12:11 CEST 2024 Ville Syrjälä <ville.syrjala@linux.intel.com> drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.
v2: Adjust gvt accordingly
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417151211.32135-1-ville.syrjala@linux.intel.com
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| /linux/drivers/gpu/drm/i915/gvt/ |
| H A D | handlers.c | diff 8034945d1a5e56f7eb1885cdd21801f93153b5a6 Wed Apr 17 17:12:11 CEST 2024 Ville Syrjälä <ville.syrjala@linux.intel.com> drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.
v2: Adjust gvt accordingly
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417151211.32135-1-ville.syrjala@linux.intel.com
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