Searched hist:"1014 f7eff9a1d4f3f796c83e933adf2462c79005" (Results 1 – 2 of 2) sorted by relevance
/linux/sound/soc/codecs/ |
H A D | tas2552.h | diff 1014f7eff9a1d4f3f796c83e933adf2462c79005 Mon Jun 08 14:19:48 CEST 2015 Peter Ujfalusi <peter.ujfalusi@ti.com> ASoC: tas2552: Correct the PLL configuration
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should be (sampling rate * 512) in all cases. Correct the J.D calculation (the D part was incorrectly calculated). Restore PLL enable status after we are done with the configuration. Implement hardware constraint handling towards the pll_clkin: if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked. If the PLL setup does not met with this constraint, fall back to BCLK as reference clock, if BCLK fails, use the internal 1.8MHz clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
|
H A D | tas2552.c | diff 1014f7eff9a1d4f3f796c83e933adf2462c79005 Mon Jun 08 14:19:48 CEST 2015 Peter Ujfalusi <peter.ujfalusi@ti.com> ASoC: tas2552: Correct the PLL configuration
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should be (sampling rate * 512) in all cases. Correct the J.D calculation (the D part was incorrectly calculated). Restore PLL enable status after we are done with the configuration. Implement hardware constraint handling towards the pll_clkin: if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked. If the PLL setup does not met with this constraint, fall back to BCLK as reference clock, if BCLK fails, use the internal 1.8MHz clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
|