Searched full:vfmv (Results 1 – 9 of 9) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVCodeGenPrepare.cpp | 113 // vfmv.s.f v10, fa0 115 // vfmv.f.s fa0, v8
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| H A D | RISCVISelLowering.h | 166 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 175 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
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| H A D | RISCVInsertVSETVLI.cpp | 441 // For vmv.s.x and vfmv.s.f, there are only two behaviors, VL = 0 and VL > 0. in getDemanded() 446 // For vmv.s.x and vfmv.s.f, if the merge operand is *undefined*, we don't in getDemanded() 488 // A tail undefined vmv.v.i/x or vfmv.v.f with VL=1 can be treated in the in getDemanded()
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| H A D | RISCVInstrInfoV.td | 1453 (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, 1650 (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, 1654 (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
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| H A D | RISCVTargetTransformInfo.cpp | 1369 // vmv.x.i, vmv.v.x, or vfmv.v.f in getStoreImmCost()
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| H A D | RISCVISelLowering.cpp | 17398 // Combine store of vmv.x.s/vfmv.f.s to vse with VL of 1. in PerformDAGCombine() 17399 // vfmv.f.s is represented as extract element from 0. Match it late to avoid in PerformDAGCombine() 17451 // If VL is 1, we can use vfmv.s.f. in PerformDAGCombine()
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
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| /freebsd/contrib/llvm-project/clang/lib/Headers/ |
| H A D | hvx_hexagon_protos.h | 4512 Assembly Syntax: Vd32.w=vfmv(Vu32.w)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 32053 "$Vd32.w = vfmv($Vu32.w)", [all...] |