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/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
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H A Dmarvell,armada-3700-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/marvell,armada-3700-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada-3700 UART
10 - Pali Rohár <pali@kernel.org>
13 Marvell UART is a non standard UART used in some of Marvell EBU SoCs (e.g.
14 Armada-3700).
19 - marvell,armada-3700-uart
20 - marvell,armada-3700-uart-ext
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H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
32 description: label associated with this uart
34 st,hw-flow-ctrl:
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H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-im
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H A Dnvidia,tegra20-hsuart.txt1 NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
4 - compatible : should be,
5 "nvidia,tegra20-hsuart" for Tegra20,
6 "nvidia,tegra30-hsuart" for Tegra30,
7 "nvidia,tegra186-hsuart" for Tegra186,
8 "nvidia,tegra194-hsuart" for Tegra194.
10 - reg: Should contain UART controller registers location and length.
11 - interrupts: Should contain UART controller interrupts.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
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H A Domap_serial.txt1 OMAP UART controller
4 - compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers
5 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
6 - compatible : should be "ti,am654-uart" for AM654 controllers
7 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
8 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
9 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
10 - compatible : should be "ti,am4372-uart" for AM437x controllers
11 - compatible : should be "ti,am3352-uart" for AM335x controllers
12 - compatible : should be "ti,dra742-uart" for DRA7x controllers
[all …]
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
32 the UART's CTS line.
34 dcd-gpios:
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H A Dingenic,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs UART controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
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H A Dnvidia,tegra264-utc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra UTC (UART Trace Controller) client
10 - Kartik Rajput <kkartik@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
12 - Jonathan Hunter <jonathanh@nvidia.com>
15 Represents a client interface of the Tegra UTC (UART Trace Controller). The
17 UART interface. It supports up to 16 clients. Each client operates as an
[all …]
H A Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
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H A Dnvidia,tegra20-hsuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/nvidia,tegra20-hsuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-hsuart
18 - nvidia,tegra30-hsuart
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H A Dsprd-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Spreadtrum serial UART
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - items:
19 - enum:
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H A Dmediatek,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
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H A Dfsl-imx-uart.txt1 * Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
[all …]
H A Dqcom,msm-uartdm.txt3 The MSM serial UARTDM hardware is designed for high-speed use cases where the
4 transmit and/or receive channels can be offloaded to a dma-engine. From a
5 software perspective it's mostly compatible with the MSM serial UART except
9 - compatible: Should contain at least "qcom,msm-uartdm".
12 "qcom,msm-uartdm-v1.1"
13 "qcom,msm-uartdm-v1.2"
14 "qcom,msm-uartdm-v1.3"
15 "qcom,msm-uartdm-v1.4"
16 - reg: Should contain UART register locations and lengths. The first
19 "qcom,msm-uartdm-v1.3" is the only compatible value that might
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H A D8250_omap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
13 - $ref: /schemas/serial/serial.yaml#
14 - $ref: /schemas/serial/rs485.yaml#
19 - enum:
20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
[all …]
H A Dsocionext,milbeaut-usio-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/socionext,milbeaut-usio-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext Milbeaut UART controller
10 - Sugaya Taichi <sugaya.taichi@socionext.com>
13 - $ref: /schemas/serial/serial.yaml#
17 const: socionext,milbeaut-usio-uart
24 - description: RX interrupt specifier
25 - description: TX interrupt specifier
[all …]
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpc5121-psc.txt3 PSC in UART mode
4 ----------------
6 For PSC in UART mode the needed PSC serial devices
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 stdout-path = "serial0:115200n8";
14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
26 * GPIO line, however the i.MX6 UART driver assumes RX happens
27 * during TX anyway and that it only controls drive enable DE
30 rs485-rx-en-hog {
31 gpio-hog;
33 line-name = "rs485-rx-en";
34 output-low;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov920.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
[all …]
/freebsd/sys/dev/uart/
H A Duart_dev_msm.c1 /*-
27 /* Qualcomm MSM7K/8K uart driver */
39 #include <dev/uart/uart.h>
40 #include <dev/uart/uart_cpu.h>
41 #include <dev/uart/uart_cpu_fdt.h>
42 #include <dev/uart/uart_bus.h>
43 #include <dev/uart/uart_dev_msm.h>
50 bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
52 bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
57 * Low-level UART interface.
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H A Duart_dev_mvebu.c1 /*-
37 #include <dev/uart/uart.h>
38 #include <dev/uart/uart_bus.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_cpu_fdt.h>
54 #define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */
61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */
63 #define CTRL_TX_EMPT_INT (1 << 6) /* TX Empty Interrupt Enable */
64 #define CTRL_TX_RDY_INT (1 << 5) /* TX Ready Interrupt Enable */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dste-dma40.txt4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
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