Home
last modified time | relevance | path

Searched +full:sw +full:- +full:enable +full:- +full:bit (Results 1 – 25 of 237) sorted by relevance

12345678910

/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
41 st-spics,sw-enable-bit:
[all …]
H A Dspear_spics.txt17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
27 All the above bit offsets are within peripcfg register.
30 -------
[all …]
/freebsd/sys/dev/ichiic/
H A Dig4_reg.h40 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf
42 * This is a from-scratch driver under the BSD license using the Intel data
61 * Register width is 32-bits
100 #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */
[all...]
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp1 //===-- xray_mips.cpp -------------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // Implementation of MIPS-specific routines (32-bit).
13 //===----------------------------------------------------------------------===//
24 PO_SW = 0xAC000000, // sw rt, offset(sp)
52 inline static bool patchSled(const bool Enable, const uint32_t FuncId, in patchSled() argument
55 // When |Enable| == true, in patchSled()
56 // We replace the following compile-time stub (sled): in patchSled()
66 // xray_sled_n (32-bit): in patchSled()
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
33 * Producer: SW/FW
42 * Cookie field exclusively used by SW. HW ignores the contents,
46 * Field can be used by SW to for example associate the buffers
488 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20)
489 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21)
490 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22)
491 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23)
492 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24)
[all …]
/freebsd/sys/dev/e1000/
H A De1000_api.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 * e1000_init_mac_params - Initialize MAC function pointers
48 if (hw->mac.ops.init_params) { in e1000_init_mac_params()
49 ret_val = hw->mac.ops.init_params(hw); in e1000_init_mac_params()
56 ret_val = -E1000_ERR_CONFIG; in e1000_init_mac_params()
64 * e1000_init_nvm_params - Initialize NVM function pointers
74 if (hw->nvm.ops.init_params) { in e1000_init_nvm_params()
75 ret_val = hw->nvm.ops.init_params(hw); in e1000_init_nvm_params()
82 ret_val = -E1000_ERR_CONFIG; in e1000_init_nvm_params()
[all …]
H A De1000_82543.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
86 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82543()
91 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82543()
92 phy->type = e1000_phy_none; in e1000_init_phy_params_82543()
95 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82543()
96 phy->ops.power_down = e1000_power_down_phy_copper; in e1000_init_phy_params_82543()
99 phy->addr = 1; in e1000_init_phy_params_82543()
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82543()
[all …]
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
H A De1000_mac.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * Setups up the function pointers to no-op functions
49 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_ops_generic()
53 mac->ops.init_params = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
54 mac->ops.init_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
55 mac->ops.reset_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
56 mac->ops.setup_physical_interface = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
57 mac->ops.get_bus_info = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
[all …]
H A De1000_ich8lan.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
36 * 82562G-2 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
21 - system-power-controller: Indicates that this PMIC is controlling the
[all …]
/freebsd/sys/dev/igc/
H A Digc_i225.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
22 * igc_init_nvm_params_i225 - Init NVM func ptrs.
27 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
36 * Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_i225()
47 nvm->word_size = 1 << size; in igc_init_nvm_params_i225()
48 nvm->opcode_bits = 8; in igc_init_nvm_params_i225()
49 nvm->delay_usec = 1; in igc_init_nvm_params_i225()
50 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_i225()
53 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; in igc_init_nvm_params_i225()
[all …]
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-miphy28lp.txt8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
24 - reg : Address and length of the register set for the device.
25 - reg-names : The names of the register addresses corresponding to the registers
[all …]
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
34 * Producer: SW/FW
43 * Cookie field exclusively used by SW. HW ignores the contents,
47 * Field can be used by SW to for example associate the buffers
589 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(8)
590 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(9)
591 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(10)
592 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(11)
[all …]
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,imx8qxp-dc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Display Controller has a built-in interrupt controller with the following
13 * Enable bit (mask)
14 * Status bit (set by an HW event)
15 * Preset bit (can be used by SW to set status)
16 * Clear bit (used by SW to reset the status)
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
[all …]
/freebsd/contrib/ntp/util/
H A Dtg.c6 * broadcast timecode. Alternatively, it can generate the IRIG-B
24 * over the range 0-255. The signal generator by default uses WWV
26 * switches to IRIG-B format.
34 * warning bit in the WWV/H timecode, so is handy to check for correct
42 * the transmissionorder is low-order first as the frame is processed
43 * left to right. For WWV/H The leap warning L preceeds the first bit.
44 * For IRIG the on-time marker M preceeds the first (units) bit, so its
45 * code is delayed one bit and the next digit (tens) needs only three
64 #define SECOND 8000 /* one second of 125-us samples */
68 #define IRIG 1 /* IRIG-B encoder */
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dwmi.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
28 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
34 * 3. DO NOT define bit fields within structures. Implement bit fields
35 * using masks if necessary. Do not use the programming language's bit
44 * variable is already 4-byte aligned by virtue of being a u32
49 * enable HTML document generation using Doxygen.
523 BIT((svc_id) % (sizeof(u32))))
[all …]
/freebsd/sys/contrib/device-tree/Bindings/leds/backlight/
H A Drichtek,rt4831-backlight.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
20 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
23 - $ref: common.yaml#
27 const: richtek,rt4831-backlight
29 default-brightness:
33 max-brightness:
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_power.c30 ahp->ah_mcast_filter_l32_set = 0; in ar9300_wowoffload_prep()
31 ahp->ah_mcast_filter_u32_set = 0; in ar9300_wowoffload_prep()
39 if (ahp->ah_mcast_filter_l32_set != 0) { in ar9300_wowoffload_post()
41 val &= ~ahp->ah_mcast_filter_l32_set; in ar9300_wowoffload_post()
44 if (ahp->ah_mcast_filter_u32_set != 0) { in ar9300_wowoffload_post()
46 val &= ~ahp->ah_mcast_filter_u32_set; in ar9300_wowoffload_post()
50 ahp->ah_mcast_filter_l32_set = 0; in ar9300_wowoffload_post()
51 ahp->ah_mcast_filter_u32_set = 0; in ar9300_wowoffload_post()
72 ahp->ah_mcast_filter_u32_set |= (1 << pos); in ar9300_wowoffload_add_mcast_filter()
74 ahp->ah_mcast_filter_l32_set |= (1 << pos); in ar9300_wowoffload_add_mcast_filter()
[all …]
H A Dar9300_beacon.c48 (ONE_EIGHTH_TU_TO_USEC(next_beacon) - in ar9300_beacon_init()
49 ah->ah_config.ah_dma_beacon_response_time)); in ar9300_beacon_init()
51 (ONE_EIGHTH_TU_TO_USEC(next_beacon) - in ar9300_beacon_init()
52 ah->ah_config.ah_sw_beacon_response_time)); in ar9300_beacon_init()
73 /* enable timers */ in ar9300_beacon_init()
86 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; in ar9300_set_sta_beacon_timers()
88 HALASSERT(bs->bs_intval != 0); in ar9300_set_sta_beacon_timers()
91 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); in ar9300_set_sta_beacon_timers()
99 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD)); in ar9300_set_sta_beacon_timers()
101 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD)); in ar9300_set_sta_beacon_timers()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spic
[all...]
/freebsd/sys/dev/ice/
H A Dice_sched.h1 /* SPDX-License-Identifier: BSD-3-Clause */
47 * profile(s). MSB is a granularity bit and tells the granularity type
48 * 0 - LSB bits are in 64 bytes granularity
49 * 1 - LSB bits are in 1K bytes granularity
52 #define ICE_KBYTE_GRANULARITY BIT(11)
55 ((BIT(11) -
[all...]
/freebsd/sys/dev/uart/
H A Duart_dev_mu.c1 /*-
33 * - 7 or 8 bit operation.
34 * - 1 start and 1 stop bit.
35 * - No parities.
36 * - Break generation.
37 * - 8 symbols deep FIFOs for receive and transmit.
38 * - SW controlled RTS, SW readable CTS.
39 * - Auto flow control with programmable FIFO level.
40 * - 16550 like registers.
41 * - Baudrate derived from system clock.
[all …]

12345678910