Home
last modified time | relevance | path

Searched full:sv48 (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/riscv/include/
H A Dvmparam.h116 * sizes: SV32, SV39, SV48 and SV57. Only SV39 and SV48 are supported by
118 * page tables, while SV48 provides a 256TB virtual address space and uses
121 * page tables, and pmap_bootstrap() optionally switches to SV48 mode.
125 * region is used for various kernel maps. The kernel map layout in SV48 mode
136 * SV48 memory map:
H A Dcpu.h87 * so Sv48-enabled systems MUST support Sv39, etc.
H A Dpte.h45 /* Level 0 table, 512GiB per entry, SV48 only */
/freebsd/share/man/man7/
H A Darch.7276 .Bl -column -offset indent "riscv64 (Sv48)" "0x0001000000000000" "NNNU"
290 .It riscv64 (Sv48) Ta 0x0000800000000000 Ta 128TiB
291 .It riscv64c (Sv48) Ta 0x0000800000000000 Ta 128TiB
322 The RISC-V specification permits 3-level (Sv39), 4-level (Sv48), and
325 Sv48 must also support Sv39, and implementations which support Sv57 must also
326 support Sv48.
331 currently supports Sv39 and Sv48 and defaults to using Sv39.
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml75 - riscv,sv48
198 mmu-type = "riscv,sv48";
/freebsd/sys/riscv/riscv/
H A Didentcpu.c343 if (strcmp(mmu, "riscv,sv48") == 0) in parse_mmu_fdt()
460 * MMU capabilities, e.g. Sv48. in update_global_capabilities()
596 "\02Sv48" in printcpuinfo()
H A Dlocore.S136 * here and will conditionally enable Sv48 (or higher) later.
H A Dpmap.c168 * Note that these ranges are used in both SV39 and SV48 mode. In SV39 mode the
232 "translation mode, 0 = SV39, 1 = SV48");
719 /* Detect Sv48 mode. */ in pmap_create_pagetables()
725 * Sv48 mode: allocate an L0 page table to be the root. The in pmap_create_pagetables()
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml785 mmu-type = "riscv,sv48";
801 mmu-type = "riscv,sv48";
817 mmu-type = "riscv,sv48";
833 mmu-type = "riscv,sv48";