Searched +full:stih407 +full:- +full:sbc +full:- +full:syscfg (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/soc/sti/st,sti-syscon.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Patrice Chotard <patrice.chotard@foss.st.com>14 platform device-tree to point to some common configuration20 - enum:21 - st,stih407-core-syscfg22 - st,stih407-flash-syscfg23 - st,stih407-front-syscfg[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 #include "stih407-pinctrl.dtsi"7 #include <dt-bindings/mfd/st-lpc.h>8 #include <dt-bindings/phy/phy.h>9 #include <dt-bindings/reset/stih407-resets.h>10 #include <dt-bindings/interrupt-controller/irq-st.h>12 #address-cells = <1>;13 #size-cells = <1>;15 reserved-memory {16 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 #include "stih418-clock.dtsi"7 #include "stih407-family.dtsi"8 #include "stih410-pinctrl.dtsi"9 #include <dt-bindings/thermal/thermal.h>12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";18 /* u-boot puts hpen in SBC dmem at 0xa4 offset */19 cpu-release-addr = <0x94100A4>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only6 #include "st-pincfg.h"7 #include <dt-bindings/interrupt-controller/arm-gic.h>11 /* 0-5: PIO_SBC */18 /* 10-19: PIO_FRONT0 */31 /* 30-35: PIO_REAR */38 /* 40-42: PIO_FLASH */45 pin-controller-sbc@961f080 {46 #address-cells = <1>;47 #size-cells = <1>;[all …]
3 Each multi-function pin is controlled, driven and routed through the5 and multiple alternate functions(ALT1 - ALTx) that directly connect14 GPIO bank can have one of the two possible types of interrupt-wirings.20 | |----> [gpio-bank (n) ]21 | |----> [gpio-bank (n + 1)]22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]23 | |----> [gpio-bank (... )]24 |_________|----> [gpio-bank (n + 7)]28 [irqN]----> [gpio-bank (n)]33 - compatible : should be "st,stih407-<pio-block>-pinctrl"[all …]