Searched +full:sm8150 +full:- +full:usb +full:- +full:hs +full:- +full:phy (Results 1 – 3 of 3) sorted by relevance
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | qcom,dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
12 # Use the combined qcom,snps-dwc3 instead
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
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| H A D | qcom,snps-dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Describes the Qualcomm USB block, based on Synopsys DWC3.
19 const: qcom,snps-dwc3
21 - compatible
26 - enum:
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-snps-femto-v2.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/phy/phy.h>
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
114 * @phy: generic phy
115 * @base: iomapped memory space for snps hs phy
119 * @phy_reset: phy reset control
121 * @phy_initialized: if PHY has been initialized correctly
122 * @mode: contains the current mode the PHY is in
123 * @update_seq_cfg: tuning parameters for phy init
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