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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dbrcm,ns2-drd-phy.txt4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
14 - id-gpios: id gpio binding
[all …]
H A Dbrcm,ns2-drd-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Hauke Mehrtens <hauke@hauke-m.de>
12 - Rafał Miłecki <zajec5@gmail.com>
16 const: brcm,ns2-drd-phy
20 - description: DRD ICFG configurations
21 - description: DRD IDM reset
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/freebsd/sys/contrib/dev/athk/ath10k/
H A Dahb.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
17 { .compatible = "qcom,ipq4019-wifi",
30 return &ath10k_pci_priv(ar)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
75 if (ar->hw_rev == ATH10K_HW_QCA4019) in ath10k_ahb_get_num_banks()
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/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dufs-hisi.txt3 UFS nodes are defined to describe on-chip UFS hardware macro.
7 - compatible : compatible list, contains one of the following -
8 "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
10 "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
12 - reg : should contain UFS register address space & UFS SYS CTRL register address,
13 - interrupts : interrupt number
14 - clocks : List of phandle and clock specifier pairs
15 - clock-names : List of clock input name strings sorted in the same
17 - freq-table-hz : Array of <min max> operating frequencies stored in the same
22 - resets : describe reset node register
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H A Dhisilicon,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
21 - compatible
24 - $ref: ufs-common.yaml
29 - items:
30 - const: hisilicon,hi3660-ufs
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/freebsd/contrib/libcbor/src/cbor/
H A Dfloats_ctrls.h2 * Copyright (c) 2014-2020 Pavel Kalvoda <me@pavelkalvoda.com>
24 /** Is this a ctrl value?
26 * @param item A float or ctrl item
27 * @return Is this a ctrl value?
34 * @param item A float or ctrl item
80 /** Get value from a boolean ctrl item
82 * @param item A ctrl item
87 /** Constructs a new ctrl item
91 * @return Reference to the new ctrl item. The item's reference count is
127 /** Constructs new null ctrl item
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H A Dserialization.h2 * Copyright (c) 2014-2020 Pavel Kalvoda <me@pavelkalvoda.com>
53 * \rst
155 * @param item A float or ctrl
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Drzg3e-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
13 * 0 - SD0 is connected to eMMC (default)
14 * 1 - SD0 is connected to uSD0 card
17 * 0 - Select Misc. Signals routing
18 * 1 - Select LCD
21 * 0 - Select CAN routing
22 * 1 - Select PDM
26 compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
42 reg_1p8v: regulator-1p8v {
43 compatible = "regulator-fixed";
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H A Dr9a07g044l2-remi-pi.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
18 compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
36 stdout-path = "serial0:115200n8";
39 hdmi-out {
40 compatible = "hdmi-connector";
42 ddc-i2c-bus = <&i2c1>;
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g_regs.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
65 uint32_t ctrl; member
75 uint32_t rst; member
132 /* Bit-wise write enable */
136 /**** ctrl register ****/
139 * 0x1 – Select inter-macro reference clock from the left side
141 * 0x3 – Select inter-macro reference clock from the right side
156 * 0x2 – Select inter-macro reference clock input from right side
172 * 0x2 – Select inter-macro reference clock input from left side
186 * Program memory acknowledge - Only when the access
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
16 .-----. .-----.
18 .------------. '-----' '-----'
20 | | .--------+--------'
21 | .------. | .------+ child bus A, on MUX value set to 0
22 | | I2C |-|--| Mux |
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H A Di2c-mux-gpmux.txt6 .-----. .-----.
8 .------------. '-----' '-----'
10 | | .--------+--------'
11 | .------. | .------+ child bus A, on MUX value set to 0
12 | | I2C |-|--| Mux |
13 | '------' | '--+---+ child bus B, on MUX value set to 1
14 | .------. | | '----------+--------+--------.
15 | | MUX- | | | | | |
16 | | Ctrl |-|-----+ .-----. .-----. .-----.
17 | '------' | | dev | | dev | | dev |
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-hrefv60plus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href.dtsi"
9 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
10 compatible = "st-ericsson,hrefv60+", "st-ericsso
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/freebsd/sys/contrib/device-tree/src/arm64/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the subset of the 32-bit PowerPC instruction set, as used
12 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
187 // Perform FADD in round-to-zero mode.
244 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
245 // amounts. These nodes are generated by the multi-precision shift code.
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H A DPPCInstr64Bit.td1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the PowerPC 64-bit instructions. These patterns are used
10 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // 64-bit operands.
33 // to accept immediates in the range -65536..65535 for compatibility with
34 // the GNU assembler. The operand is treated as 16-bit otherwise.
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/freebsd/sys/dev/e1000/
H A De1000_vf.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
56 * e1000_init_phy_params_vf - Inits PHY params
59 * Doesn't do much - there's no PHY available to the VF.
64 hw->phy.type = e1000_phy_vf; in e1000_init_phy_params_vf()
65 hw->phy.ops.acquire = e1000_acquire_vf; in e1000_init_phy_params_vf()
66 hw->phy.ops.release = e1000_release_vf; in e1000_init_phy_params_vf()
72 * e1000_init_nvm_params_vf - Inits NVM params
75 * Doesn't do much - there's no NVM available to the VF.
80 hw->nvm.type = e1000_nvm_none; in e1000_init_nvm_params_vf()
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: regulator-pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8226-samsung-matisse-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on
11 #include <dt-bindings/input/input.h>
14 /delete-node/ &adsp_region;
15 /delete-node/ &mba_region;
16 /delete-node/ &mpss_region;
17 /delete-node/ &smem_region;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 stdout-path = "display0";
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/freebsd/sys/dev/mlx5/mlx5_fpga/
H A Dmlx5fpga_conn.c1 /*-
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
52 if (unlikely(!buf->sg[0].data)) in mlx5_fpga_conn_map_buf()
55 dma_device = &conn->fdev->mdev->pdev->dev; in mlx5_fpga_conn_map_buf()
56 buf->sg[0].dma_addr = dma_map_single(dma_device, buf->sg[0].data, in mlx5_fpga_conn_map_buf()
57 buf->sg[0].size, buf->dma_dir); in mlx5_fpga_conn_map_buf()
58 err = dma_mapping_error(dma_device, buf->sg[0].dma_addr); in mlx5_fpga_conn_map_buf()
60 mlx5_fpga_warn(conn->fdev, "DMA error on sg 0: %d\n", err); in mlx5_fpga_conn_map_buf()
61 err = -ENOMEM; in mlx5_fpga_conn_map_buf()
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/freebsd/sys/dev/sound/pci/
H A Des137x.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause AND BSD-4-Clause
30 /*-
128 #define ES_BLK_ALIGN (~(ES_BLK_MIN - 1))
148 * 32bit Ensoniq Configuration (es->escfg).
149 * ----------------------------------------
151 * +-------+--------+------+------+---------+--------+---------+---------+
153 * +-------+--------+------+------+---------+--------+---------+---------+
157 * +-------+--------+------+------+---------+--------+---------+---------+
200 * DAC 1/2 configuration through kernel hint - hint.pcm.<unit>.dac="val"
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8998-fxtec-pro1.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 chassis-type = "handset";
21 qcom,board-id = <0x02000b 0x10>;
29 * Until we hook up type-c detection, we
32 extcon_usb: extcon-usb {
33 compatible = "linux,extcon-usb-gpio";
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