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/linux/drivers/reset/
H A Dreset-ti-syscon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI SYSCON regmap reset driver
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/ti-syscon.h>
20 * struct ti_syscon_reset_control - reset control structure
21 * @assert_offset: reset assert control register offset from syscon base
22 * @assert_bit: reset assert bit in the reset assert control register
23 * @deassert_offset: reset deassert control register offset from syscon base
24 * @deassert_bit: reset deassert bit in the reset deassert control register
[all …]
H A Dreset-pistachio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pistachio SoC Reset Controller driver
14 #include <linux/reset-controller.h>
18 #include <dt-bindings/reset/pistachio-resets.h>
59 return -EINVAL; in pistachio_reset_shift()
67 u32 mask; in pistachio_reset_assert() local
74 mask = BIT(shift); in pistachio_reset_assert()
76 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
77 mask, mask); in pistachio_reset_assert()
84 u32 mask; in pistachio_reset_deassert() local
[all …]
H A Dreset-a10sr.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Reset driver for Altera Arria10 MAX5 System Resource Chip
7 * Adapted from reset-socfpga.c
11 #include <linux/mfd/altera-a10sr.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
40 return -EINVAL; in a10sr_reset_shift()
49 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_update() local
52 return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); in a10sr_reset_update()
73 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_status() local
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm33xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
17 #include "prm-regbits-33xx.h"
31 /* Read-modify-write a register in PRM. Caller must lock */
32 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_prm_rmw_reg_bits() argument
37 v &= ~mask; in am33xx_prm_rmw_reg_bits()
45 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
47 * @shift: register bit shift corresponding to the reset line to check
54 * -EINVAL upon parameter error.
69 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
[all …]
H A Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
76 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, in omap4_prminst_rmw_inst_reg_bits() argument
82 v &= ~mask; in omap4_prminst_rmw_inst_reg_bits()
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
[all …]
H A Dprm2xxx_3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
24 * @shift: register bit shift corresponding to the reset line to check
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
41 * @shift: register bit shift corresponding to the reset line to assert
47 * reset line to be asserted / deasserted in order to fully enable the
48 * IP. These modules may have multiple hard-reset lines that reset
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/linux/sound/soc/intel/avs/
H A Ddsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2022 Intel Corporation
20 u32 value, mask, reg; in avs_dsp_core_power() local
26 mask = AVS_ADSPCS_SPA_MASK(core_mask); in avs_dsp_core_power()
27 value = power ? mask : 0; in avs_dsp_core_power()
29 snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value); in avs_dsp_core_power()
33 mask = AVS_ADSPCS_CPA_MASK(core_mask); in avs_dsp_core_power()
34 value = power ? mask : 0; in avs_dsp_core_power()
37 reg, (reg & mask) == value, in avs_dsp_core_power()
41 dev_err(adev->dev, "core_mask %d power %s failed: %d\n", in avs_dsp_core_power()
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/linux/drivers/media/pci/cx18/
H A Dcx18-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
27 * HVR-1600 GPIO pins, courtesy of Hauppauge:
29 * gpio0: zilog ir process reset pin
31 * gpio12: cx24227 reset pin
32 * gpio13: cs5345 reset pin
[all …]
/linux/include/linux/pds/
H A Dpds_intr.h1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
10 * device units. Use @identity->intr_coal_mult
11 * and @identity->intr_coal_div to convert from
24 * interrupt. Reset value: 0
25 * @mask: Interrupt mask. When @mask=1 the interrupt
27 * @mask=0 the interrupt resource will send an
30 * Reset value: 1
42 * @unmask -- When this bit is written with a 1
43 * the interrupt resource will set mask=0.
44 * @coal_timer_reset -- When this
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dsyscon-reboot.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON mapped register reset driver
10 - Sebastian Reichel <sre@kernel.org>
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
16 mask defined in the reboot node. Default will be little endian mode, 32 bit
18 parental dt-node. So the SYSCON reboot node should be represented as a
[all …]
/linux/drivers/clk/baikal-t1/
H A Dccu-rst.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CCU Resets interface driver
11 #define pr_fmt(fmt) "bt1-ccu-rst: " fmt
19 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/bt1-ccu.h>
24 #include "ccu-rst.h"
49 .mask = BIT(_ofs), \
56 .mask = BIT(_ofs), \
62 unsigned int mask; member
66 * Each AXI-bus clock divider is equipped with the corresponding clock-consumer
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/linux/drivers/input/misc/
H A Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
32 /* Regulator control registers for shutdown/reset */
52 /* Buck TEST2 registers for shutdown/reset */
71 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
107 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
117 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
129 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local
130 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
132 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Daspeed,ast2400-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
29 aspeed,reset-type:
32 - cpu
[all …]
/linux/include/linux/input/
H A Dadp5589.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright 2010-2011 Analog Devices Inc.
47 #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1)
76 #define ADP5585_GPIMAPSIZE_MAX (ADP5585_GPI_PIN_END - ADP5585_GPI_PIN_BASE + 1)
110 /* ADP5589 Mask Bits:
114 * ---------------- BIT ------------------
127 /* ADP5585 Mask Bits:
131 * ---- BIT -- -----------
149 unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */
158 unsigned char reset_cfg; /* Reset config */
[all …]
/linux/drivers/reset/starfive/
H A Dreset-starfive-jh71x0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH71X0 SoCs
12 #include <linux/reset-controller.h>
15 #include "reset-starfive-jh71x0.h"
19 /* protect registers against concurrent read-modify-write */
37 u32 mask = BIT(id % 32); in jh71x0_reset_update() local
38 void __iomem *reg_assert = data->assert + offset * sizeof(u32); in jh71x0_reset_update()
39 void __iomem *reg_status = data->status + offset * sizeof(u32); in jh71x0_reset_update()
40 u32 done = data->asserted ? data->asserted[offset] & mask : 0; in jh71x0_reset_update()
46 done ^= mask; in jh71x0_reset_update()
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dti-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
16 is mostly used for interaction between module and Power, Reset and Clock
31 pattern: "^target-module(@[0-9a-f]+)?$"
35 - items:
36 - enum:
37 - ti,sysc-omap2
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
140 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk)
142 * The application uses this bit to mask or unmask the interrupt
[all …]
/linux/arch/mips/include/asm/sn/sn0/
H A Dhubni.h8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
28 #define NI_PORT_RESET 0x600008 /* Reset the network interface */
70 * NI_STATUS_REV_ID mask and shift definitions
79 #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
102 /* NI_PORT_RESET mask definitions */
104 #define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105 #define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106 #define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
108 /* NI_PROTECTION mask and shift definitions */
112 /* NI_GLOBAL_PARMS mask and shift definitions */
[all …]
/linux/drivers/mfd/
H A Dqcom-pm8008.c1 // SPDX-License-Identifier: GPL-2.0-only
73 .mask = (_mask), \
115 buf[POLARITY_HI_INDEX][idx] &= ~irq_data->mask; in pm8008_set_type_config()
116 buf[POLARITY_LO_INDEX][idx] |= irq_data->mask; in pm8008_set_type_config()
121 buf[POLARITY_HI_INDEX][idx] |= irq_data->mask; in pm8008_set_type_config()
122 buf[POLARITY_LO_INDEX][idx] &= ~irq_data->mask; in pm8008_set_type_config()
126 buf[POLARITY_HI_INDEX][idx] |= irq_data->mask; in pm8008_set_type_config()
127 buf[POLARITY_LO_INDEX][idx] |= irq_data->mask; in pm8008_set_type_config()
131 return -EINVAL; in pm8008_set_type_config()
135 buf[SET_TYPE_INDEX][idx] |= irq_data->mask; in pm8008_set_type_config()
[all …]
H A Ducb1x00-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mfd/ucb1x00-core.c
11 * to be used on other non-MCP-enabled hardware platforms.
35 * ucb1x00_io_set_dir - set IO direction
54 spin_lock_irqsave(&ucb->io_lock, flags); in ucb1x00_io_set_dir()
55 ucb->io_dir |= out; in ucb1x00_io_set_dir()
56 ucb->io_dir &= ~in; in ucb1x00_io_set_dir()
58 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); in ucb1x00_io_set_dir()
59 spin_unlock_irqrestore(&ucb->io_lock, flags); in ucb1x00_io_set_dir()
63 * ucb1x00_io_write - set or clear IO outputs
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
41 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
52 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
57 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
59 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
61 ctx->name, score, in client_mark_guilty()
62 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
73 if (intel_context_is_closed(rq->context)) in mark_guilty()
77 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
[all …]
H A Dselftest_reset.c1 // SPDX-License-Identifier: MIT
19 intel_engine_mask_t mask, in __igt_reset_stolen() argument
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
34 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
43 return -ENOMEM; in __igt_reset_stolen()
47 err = -ENOMEM; in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
62 if (!(mask & engine->mask)) in __igt_reset_stolen()
83 dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT); in __igt_reset_stolen()
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
31 reset-names:
33 - const: mcu_rst
34 - const: hold_boot
[all …]
/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c25 { .compatible = "fsl,mpc5200-xlb", },
26 { .compatible = "mpc5200-xlb", },
30 { .compatible = "fsl,mpc5200-immr", },
31 { .compatible = "fsl,mpc5200b-immr", },
32 { .compatible = "simple-bus", },
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
77 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
81 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
110 { .compatible = "fsl,mpc5200-gpt", },
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_device.c7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
33 dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); in lio_cn6xxx_soft_reset()
45 dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); in lio_cn6xxx_soft_reset()
49 dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); in lio_cn6xxx_soft_reset()
59 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_enable_error_reporting()
61 dev_err(&oct->pci_dev->dev, "PCI-E Link error detected: 0x%08x\n", in lio_cn6xxx_enable_error_reporting()
67 dev_dbg(&oct->pci_dev->dev, "Enabling PCI-E error reporting..\n"); in lio_cn6xxx_enable_error_reporting()
68 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_enable_error_reporting()
78 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mps()
[all …]

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