Home
last modified time | relevance | path

Searched +full:qe +full:- +full:firmware (Results 1 – 25 of 31) sorted by relevance

12

/linux/drivers/soc/fsl/qe/
H A Dqe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
11 * QUICC Engine (QE).
30 #include <soc/fsl/qe/immap_qe.h>
31 #include <soc/fsl/qe/qe.h>
50 static phys_addr_t qebase = -1;
54 struct device_node *qe; in qe_get_device_node() local
57 * Newer device trees have an "fsl,qe" compatible property for the QE in qe_get_device_node()
60 qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); in qe_get_device_node()
61 if (qe) in qe_get_device_node()
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module (QE)
10 - Frank Li <Frank.Li@nxp.com>
13 This represents qe module that is installed on PowerQUICC II Pro.
20 the "root" qe node, using the common properties from there.
21 The description below applies to the qe of MPC8360 and
27 - const: fsl,qe
[all …]
H A Dfsl,qe-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module Firmware Node
10 - Frank Li <Frank.Li@nxp.com>
13 This node defines a firmware binary that is embedded in the device tree, for
14 the purpose of passing the firmware from bootloader to the kernel, or from
17 The firmware node itself contains the firmware binary contents, a compatible
18 property, and any firmware-specific properties. The node should be placed
[all …]
H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE QUICC Multichannel Controller (QMC)
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dfirmware.txt1 * Uploaded QE firmware
3 If a new firmware has been uploaded to the QE (usually by the
4 boot loader), then a 'firmware' child node should be added to the QE
5 node. This node provides information on the uploaded firmware that
9 - id: The string name of the firmware. This is taken from the 'id'
10 member of the qe_firmware structure of the uploaded firmware.
12 firmware they want is already present.
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
[all …]
/linux/include/soc/fsl/qe/
H A Dqe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * QUICC Engine (QE) external definitions and structure.
21 #include <soc/fsl/qe/immap_qe.h>
28 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
87 /* Export QE common operations */
112 return -ENOSYS; in cpm_muram_alloc()
118 return -ENOSYS; in devm_cpm_muram_alloc()
128 return -ENOSYS; in cpm_muram_alloc_fixed()
135 return -ENOSYS; in devm_cpm_muram_alloc_fixed()
145 return -ENOSYS; in cpm_muram_offset()
[all …]
/linux/Documentation/arch/powerpc/
H A Dqe_firmware.rst2 Freescale QUICC Engine Firmware Uploading
10 I - Software License for Firmware
12 II - Microcode Availability
14 III - Description and Terminology
16 IV - Microcode Programming Details
18 V - Firmware Structure Layout
20 VI - Sample Code for Creating Firmware Files
25 November 30, 2007: Rev 1.0 - Initial version
27 I - Software License for Firmware
30 Each firmware file comes with its own software license. For information on
[all …]
/linux/drivers/tty/serial/
H A Ducc_uart.c1 // SPDX-License-Identifier: GPL-2.0
12 * If Soft-UART support is needed but not already present, then this driver
13 * will request and upload the "Soft-UART" microcode upon probe. The
30 #include <linux/dma-mapping.h>
32 #include <soc/fsl/qe/ucc_slow.h>
34 #include <linux/firmware.h>
42 * The GUMR flag for Soft UART. This would normally be defined in qe.h,
43 * but Soft-UART is a hack and we want to keep everything related to it in
46 #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
49 * soft_uart is 1 if we need to use Soft-UART mode
[all …]
/linux/drivers/net/ethernet/freescale/
H A Ducc_geth.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
12 * - Rearrange code and style fixes
22 #include <soc/fsl/qe/immap_qe.h>
23 #include <soc/fsl/qe/qe.h>
25 #include <soc/fsl/qe/ucc.h>
26 #include <soc/fsl/qe/ucc_fast.h>
28 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
41 u8 res0[0x100 - sizeof(struct ucc_fast)];
46 u32 hafdup; /* half-duplex reg. */
[all …]
H A Ducc_geth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
9 * QE UCC Gigabit Ethernet Driver
26 #include <linux/dma-mapping.h>
42 #include <soc/fsl/qe/immap_qe.h>
43 #include <soc/fsl/qe/qe.h>
44 #include <soc/fsl/qe/ucc.h>
45 #include <soc/fsl/qe/ucc_fast.h>
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
70 } debug = { -1 };
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp1025twr.dtsi2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
48 bank-width = <2>;
49 device-width = <1>;
53 /* 256KB for Vitesse 7385 Switch firmware */
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
79 /* 256KB for QE ucode firmware*/
[all …]
H A Dp1025rdb_36b.dts2 * P1025 RDB Device Tree Source (36-bit address map)
35 /include/ "p1021si-pre.dtsi"
86 qe: qe@fffe80000 { label
87 status = "disabled"; /* no firmware loaded */
93 /include/ "p1021si-post.dtsi"
H A Dp1021rdb-pc.dtsi2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 /* 256KB for Vitesse 7385 Switch firmware */
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 256KB for QE ucode firmware*/
[all …]
H A Dp1025rdb_32b.dts2 * P1025 RDB Device Tree Source (32-bit address map)
35 /include/ "p1021si-pre.dtsi"
86 qe: qe@ffe80000 { label
89 brg-frequency = <0>;
90 bus-frequency = <0>;
91 status = "disabled"; /* no firmware loaded */
96 rx-clock-name = "clk12";
97 tx-clock-name = "clk9";
98 pio-handle = <&pio1>;
99 phy-handle = <&qe_phy0>;
[all …]
H A Dmpc8569mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
45 device-width = <1>;
[all …]
H A Dp1021mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "p1021si-pre.dtsi"
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "fsl,p1021-fcm-nand",
35 "fsl,elbc-fcm-nand";
40 /* 1MB for u-boot Bootloader Image */
42 label = "NAND (RO) U-Boot Image";
43 read-only;
50 read-only;
[all …]
H A Dp1025rdb.dtsi2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 /* 256KB for Vitesse 7385 Switch firmware */
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
[all …]
/linux/drivers/soc/fsl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 source "drivers/soc/fsl/qe/Kconfig"
16 enabling, power-onreset(POR) configuration monitoring, alternate
44 firmware logs.
51 (Run Control and Power Management), which performs all device-level
/linux/drivers/scsi/bfa/
H A Dbfa_fcs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
30 struct bfad_s *bfad = fcs->bfad; in bfa_fcs_exit_comp()
32 complete(&bfad->comp); in bfa_fcs_exit_comp()
41 bfa_sm_send_event(&fcs->fabric, BFA_FCS_FABRIC_SM_CREATE); in bfa_fcs_init()
50 * FCS update cfg - reset the pwwn/nwwn of fabric base logical port
51 * with values learned during bfa_init firmware GETATTR REQ.
56 struct bfa_fcs_fabric_s *fabric = &fcs->fabric; in bfa_fcs_update_cfg()
[all …]
H A Dbfad.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
21 #include <linux/firmware.h>
47 int bfa_linkup_delay = -1;
55 /* Firmware releate
[all...]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_ioc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
21 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
23 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
24 #define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
25 #define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
27 ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc))
29 ((__ioc)->ioc_hwif->ioc_sync_start(__ioc))
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 #include <linux/firmware.h>
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
144 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
154 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-
3486 struct ch_sched_queue qe = { 0 }; cxgb_set_tx_maxrate() local
[all...]
/linux/drivers/scsi/elx/libefc_sli/
H A Dsli4.c1 // SPDX-License-Identifier: GPL-2.0
8 * All common (i.e. transport-independent) SLI-4 functions are implemented
35 * sli_config_cmd_init() - Write a SLI_CONFIG command to the provided buffer.
40 * @dma: DMA buffer for non-embedded commands.
50 if (length > sizeof(config->payload.embed) && !dma) { in sli_config_cmd_init()
60 config->hdr.command = SLI4_MBX_CMD_SLI_CONFIG; in sli_config_cmd_init()
63 config->dw1_flags = cpu_to_le32(flags); in sli_config_cmd_init()
64 config->payload_len = cpu_to_le32(length); in sli_config_cmd_init()
65 return config->payload.embed; in sli_config_cmd_init()
70 config->dw1_flags = cpu_to_le32(flags); in sli_config_cmd_init()
[all …]
/linux/drivers/scsi/aacraid/
H A Dcommsup.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
42 * fib_map_alloc - allocate the fib objects
46 * talk to the Adaptec firmware.
51 dev->max_cmd_size = AAC_MAX_NATIVE_SIZE; in fib_map_alloc()
55 &dev->pdev->dev, dev->max_cmd_size, dev->scsi_host_ptr->can_queue, in fib_map_alloc()
56 AAC_NUM_MGT_FIB, &dev->hw_fib_pa)); in fib_map_alloc()
57 dev->hw_fib_va = dma_alloc_coherent(&dev->pdev->dev, in fib_map_alloc()
[all …]

12