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4 $id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#10 The Andes machine-level timer device (PLMT0) provides machine-level timer13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is24 - const: andestech,plmt033 Specifies which harts are connected to the PLMT0. Each item must points35 PLMT0 supports 1 hart up to 32 harts.47 compatible = "andestech,qilai-plmt", "andestech,plmt0";
131 compatible = "andestech,qilai-plmt", "andestech,plmt0";