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Searched +full:pll1 +full:- +full:div2 (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
39 - fsl,p3041-clockgen
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/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-shx3.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-shx3.c
5 * SH-X3 support for the clock framework
7 * Copyright (C) 2006-2007 Renesas Technology Corp.
8 * Copyright (C) 2006-2007 Renesas Solutions Corp.
9 * Copyright (C) 2006-2010 Paul Mundt
28 /* PLL1 has a fixed x72 multiplier. */ in pll_recalc()
29 return clk->parent->rate * 72; in pll_recalc()
47 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
51 .divisors = div2,
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H A Dclock-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
30 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1, in pll_recalc()
35 return clk->parent->rate * multiplier; in pll_recalc()
53 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
57 .divisors = div2,
58 .nr_divisors = ARRAY_SIZE(div2),
139 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
140 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
141 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
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/linux/drivers/clk/
H A Dclk-npcm8xx.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
24 #include <soc/nuvoton/clock-npcm8xx.h>
92 { "pll1", { .index = 0 }, NPCM8XX_PLLCON1, 0 },
190 { NPCM8XX_CLKDIV1, 21, 5, "pre_adc", &npcm8xx_muxes[6].hw, CLK_DIVIDER_READ_ONLY, 0, -1 },
237 val = readl_relaxed(pll->pllcon); in npcm8xx_clk_pll_recalc_rate()
265 return ERR_PTR(-ENOMEM); in npcm8xx_clk_register_pll()
273 pll->pllcon = pllcon; in npcm8xx_clk_register_pll()
274 pll->hw.init = &init; in npcm8xx_clk_register_pll()
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H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
143 * this specific clock. Otherwise, set to -1.
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H A Dclk-versaclock3.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
85 #define VC3_DIV_MASK(width) ((1 << (width)) - 1)
128 VC3_SE1_MUX = VC3_SE1 - 1,
129 VC3_SE2_MUX = VC3_SE2 - 1,
130 VC3_SE3_MUX = VC3_SE3 - 1,
131 VC3_DIFF1_MUX = VC3_DIFF1 - 1,
132 VC3_DIFF2_MUX = VC3_DIFF2 - 1,
222 const struct vc3_clk_data *pfd_mux = vc3->data; in vc3_pfd_mux_get_parent()
225 regmap_read(vc3->regmap, pfd_mux->offs, &src); in vc3_pfd_mux_get_parent()
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/linux/arch/arm/boot/dts/st/
H A Dstih410-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih410-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
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H A Dstih418-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih418-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
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/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
23 #include "reset-stm32.h"
171 "ck_hse", "pll4_r", "clk-hse-div2"
397 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
400 cfg->name, in _clk_hw_register_gate()
401 cfg->parent_name, in _clk_hw_register_gate()
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