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Searched +full:pll +full:- +full:out (Results 1 – 25 of 595) sorted by relevance

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/linux/drivers/clk/at91/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
58 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
61 pll->characteristics; in clk_pll_prepare()
62 u8 id = pll->id; in clk_pll_prepare()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dti,pcm512x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dai-common.yaml#
18 - ti,pcm5121
19 - ti,pcm5122
20 - ti,pcm5141
21 - ti,pcm5142
22 - ti,pcm5242
[all …]
/linux/drivers/clk/keystone/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
29 * @phy_pllm: Physical address of PLLM in pll controller. Used when
31 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
32 * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
33 * or PA PLL available on keystone2. These PLLs are controlled by
[all …]
/linux/drivers/clk/tegra/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
42 - silabs,si5340
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-pllfh.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
14 #include "clk-mtk.h"
15 #include "clk-pllfh.h"
16 #include "clk-fhctl.h"
22 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in to_mtk_fh() local
24 return container_of(pll, struct mtk_fh, clk_pll); in to_mtk_fh()
30 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
27 #include <sound/omap-hdmi-audio.h>
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
56 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
97 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
100 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
161 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
163 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
[all …]
H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
116 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
173 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
175 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
182 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
184 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
[all …]
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define DSS_SUBSYS_NAME "PLL"
30 int dss_pll_register(struct dss_pll *pll) in dss_pll_register() argument
36 dss_plls[i] = pll; in dss_pll_register()
41 return -EBUSY; in dss_pll_register()
44 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
49 if (dss_plls[i] == pll) { in dss_pll_unregister()
61 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0) in dss_pll_find()
68 int dss_pll_enable(struct dss_pll *pll) in dss_pll_enable() argument
72 r = clk_prepare_enable(pll->clkin); in dss_pll_enable()
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PLL clock Driver
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
20 #include "clk-sg2042.h"
24 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
25 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
26 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
27 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
28 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27 #include "pll.h"
31 #include <subdev/bios/pll.h>
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
108 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll() argument
[all …]
H A Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
49 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
54 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
66 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp()
68 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
72 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
73 pll-> in gk20a_pllg_read_mnp()
65 gk20a_pllg_read_mnp(struct gk20a_clk * clk,struct gk20a_pll * pll) gk20a_pllg_read_mnp() argument
77 gk20a_pllg_write_mnp(struct gk20a_clk * clk,const struct gk20a_pll * pll) gk20a_pllg_write_mnp() argument
89 gk20a_pllg_calc_rate(struct gk20a_clk * clk,struct gk20a_pll * pll) gk20a_pllg_calc_rate() argument
102 gk20a_pllg_calc_mnp(struct gk20a_clk * clk,unsigned long rate,struct gk20a_pll * pll) gk20a_pllg_calc_mnp() argument
215 struct gk20a_pll pll; gk20a_pllg_slide() local
296 gk20a_pllg_program_mnp(struct gk20a_clk * clk,const struct gk20a_pll * pll) gk20a_pllg_program_mnp() argument
335 gk20a_pllg_program_mnp_slide(struct gk20a_clk * clk,const struct gk20a_pll * pll) gk20a_pllg_program_mnp_slide() argument
465 struct gk20a_pll pll; gk20a_clk_read() local
550 struct gk20a_pll pll; gk20a_clk_fini() local
[all...]
H A Dgm20b.c19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
90 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
91 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
100 .coeff_slope = -165230,
161 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp()
163 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
164 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
167 gk20a_pllg_read_mnp(&clk->bas in gm20b_pllg_read_mnp()
160 gm20b_pllg_read_mnp(struct gm20b_clk * clk,struct gm20b_pll * pll) gm20b_pllg_read_mnp() argument
173 gm20b_pllg_write_mnp(struct gm20b_clk * clk,const struct gm20b_pll * pll) gm20b_pllg_write_mnp() argument
270 struct gm20b_pll pll; gm20b_pllg_slide() local
360 gm20b_pllg_program_mnp(struct gm20b_clk * clk,const struct gk20a_pll * pll) gm20b_pllg_program_mnp() argument
433 gm20b_pllg_program_mnp_slide(struct gm20b_clk * clk,const struct gk20a_pll * pll) gm20b_pllg_program_mnp_slide() argument
488 gm20b_dvfs_calc_safe_pll(struct gm20b_clk * clk,struct gk20a_pll * pll) gm20b_dvfs_calc_safe_pll() argument
727 struct gk20a_pll pll; gm20b_clk_fini() local
[all...]
H A Dmcp77.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 #include "pll.h"
29 #include <subdev/bios/pll.h>
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
[all …]
H A Dnv50.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 #include "pll.h"
29 #include <subdev/bios/pll.h>
34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
69 nvkm_error(subdev, "ref: bad pll %06x\n", base); in read_pll_src()
[all …]
/linux/drivers/clk/baikal-t1/
H A Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
107 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_enable() local
114 return -EINVAL; in ccu_pll_enable()
[all …]
/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
42 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
49 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
50 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
51 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
52 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
53 #define WRPCR_ODF GENMASK(17, 16) /* pll Outpu
[all...]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
6 #define DSS_SUBSYS_NAME "PLL"
28 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll) in dss_pll_register() argument
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
43 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
65 /* Fractional PLL operating modes */
78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
80 return readl(pll->base + reg); in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
85 writel(val, pll->base + reg); in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
107 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
[all …]
/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-only
19 wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); in wl1251_boot_target_enable_interrupts()
40 /* 1.2 check pWhalBus->uSelfClearTime if the in wl1251_boot_soft_reset()
43 return -1; in wl1251_boot_soft_reset()
106 /* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */ in wl1251_boot_init_seq()
110 /* PG 1.2: Set the BB PLL stable time to be 1000usec in wl1251_boot_init_seq()
118 * PG 1.2: set the clock request time to be ref_clk_settling_time - in wl1251_boot_init_seq()
122 tmp = init_data - 0x21; in wl1251_boot_init_seq()
127 /* set BB PLL configurations in RF AFE */ in wl1251_boot_init_seq()
137 * change RF PLL and BB PLL divider for VCO clock and adjust VCO in wl1251_boot_init_seq()
[all …]
/linux/drivers/media/i2c/ccs/
H A Dccs-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/ccs/ccs-core.c
8 * Copyright (C) 2010--2012 Nokia Corporation
13 * Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
27 #include <linux/v4l2-mediabus.h>
28 #include <media/v4l2-cc
376 struct ccs_pll *pll = &sensor->pll; ccs_pll_configure() local
435 ccs_pll_try(struct ccs_sensor * sensor,struct ccs_pll * pll) ccs_pll_try() argument
488 struct ccs_pll *pll = &sensor->pll; ccs_pll_update() local
1061 struct ccs_pll *pll = &sensor->pll; ccs_get_mbus_formats() local
[all...]
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
[all …]
/linux/sound/soc/codecs/
H A Dtlv320aic32x4-clk.c1 /* SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
26 * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
49 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); in clk_aic32x4_pll_prepare() local
51 return regmap_update_bits(pll->regmap, AIC32X4_PLLPR, in clk_aic32x4_pll_prepare()
57 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); in clk_aic32x4_pll_unprepare() local
59 regmap_update_bits(pll->regmap, AIC32X4_PLLPR, in clk_aic32x4_pll_unprepare()
65 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); in clk_aic32x4_pll_is_prepared() local
70 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); in clk_aic32x4_pll_is_prepared()
77 static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll, in clk_aic32x4_pll_get_muldiv() argument
[all …]
/linux/drivers/media/i2c/
H A Daptina-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
[all …]

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