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/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
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H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
35 /* Skip if already enabled or in FSM mode */ in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
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/linux/drivers/media/i2c/
H A Daptina-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c6 * to deal in the Software without restriction, including without limitation
11 * The above copyright notice and this permission notice shall be included in
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
91 if (adev->family == AMDGPU_FAMILY_SI) in amdgpu_pll_get_fb_ref_div()
108 * amdgpu_pll_compute - compute PLL paramaters
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/linux/drivers/clk/keystone/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
27 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
29 * @phy_pllm: Physical address of PLLM in pll controller. Used when
31 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
32 * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
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/linux/Documentation/devicetree/bindings/sound/
H A Dti,pcm512x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dai-common.yaml#
18 - ti,pcm5121
19 - ti,pcm5122
20 - ti,pcm5141
21 - ti,pcm5142
22 - ti,pcm5242
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/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PLL clock Driver
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
20 #include "clk-sg2042.h"
22 /* Registers defined in SYS_CTRL */
24 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
25 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
26 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
27 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
40 if (display->platform.pantherlake) { in intel_encoder_is_c10phy()
41 if (display->platform.pantherlake_wildcatlake) in intel_encoder_is_c10phy()
47 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
70 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
83 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
93 XELPDP_PORT_MSGBUS_TIMER(display, encoder->por in intel_cx0_program_msgbus_timer()
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
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/linux/drivers/clk/zynq/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq PLL driver
10 #include <linux/clk-provider.h>
15 * struct zynq_pll - pll clock
16 * @hw: Handle between common and hardware-specific interfaces
17 * @pll_ctrl: PLL control register
18 * @pll_status: PLL status register
20 * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
45 * zynq_pll_round_rate() - Round a clock frequency
46 * @hw: Handle between common and hardware-specific interfaces
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
6 * to deal in the Software without restriction, including without limitation
11 * The above copyright notice and this permission notice shall be included in
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
49 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
54 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
66 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp()
65 gk20a_pllg_read_mnp(struct gk20a_clk * clk,struct gk20a_pll * pll) gk20a_pllg_read_mnp() argument
77 gk20a_pllg_write_mnp(struct gk20a_clk * clk,const struct gk20a_pll * pll) gk20a_pllg_write_mnp() argument
89 gk20a_pllg_calc_rate(struct gk20a_clk * clk,struct gk20a_pll * pll) gk20a_pllg_calc_rate() argument
102 gk20a_pllg_calc_mnp(struct gk20a_clk * clk,unsigned long rate,struct gk20a_pll * pll) gk20a_pllg_calc_mnp() argument
215 struct gk20a_pll pll; gk20a_pllg_slide() local
296 gk20a_pllg_program_mnp(struct gk20a_clk * clk,const struct gk20a_pll * pll) gk20a_pllg_program_mnp() argument
335 gk20a_pllg_program_mnp_slide(struct gk20a_clk * clk,const struct gk20a_pll * pll) gk20a_pllg_program_mnp_slide() argument
465 struct gk20a_pll pll; gk20a_clk_read() local
550 struct gk20a_pll pll; gk20a_clk_fini() local
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H A Dgm20b.c6 * to deal in the Software without restriction, including without limitation
11 * The above copyright notice and this permission notice shall be included in
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
90 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
91 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-
160 gm20b_pllg_read_mnp(struct gm20b_clk * clk,struct gm20b_pll * pll) gm20b_pllg_read_mnp() argument
173 gm20b_pllg_write_mnp(struct gm20b_clk * clk,const struct gm20b_pll * pll) gm20b_pllg_write_mnp() argument
270 struct gm20b_pll pll; gm20b_pllg_slide() local
360 gm20b_pllg_program_mnp(struct gm20b_clk * clk,const struct gk20a_pll * pll) gm20b_pllg_program_mnp() argument
433 gm20b_pllg_program_mnp_slide(struct gm20b_clk * clk,const struct gk20a_pll * pll) gm20b_pllg_program_mnp_slide() argument
488 gm20b_dvfs_calc_safe_pll(struct gm20b_clk * clk,struct gk20a_pll * pll) gm20b_dvfs_calc_safe_pll() argument
727 struct gk20a_pll pll; gm20b_clk_fini() local
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H A Dgt215.c6 * to deal in the Software without restriction, including without limitation
11 * The above copyright notice and this permission notice shall be included in
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "pll.h"
31 #include <subdev/bios/pll.h>
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
13 can be found in [1].
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
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H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
26 in turn can be directed to any of the 10 (or 4) outputs through a divider.
27 The internal structure of the clock generators can be found in [2].
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H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
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H A Dmediatek,mt8196-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guangjie Song <guangjie.song@mediatek.com>
11 - Laura Nao <laura.nao@collabora.com>
14 The clock architecture in MediaTek SoCs is structured like below:
15 PLLs -->
16 dividers -->
18 -->
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/linux/include/linux/clk/
H A Drenesas.h1 /* SPDX-License-Identifier: GPL-2.0+
13 #include <linux/clk-provider.h>
39 * struct rzv2h_pll_limits - PLL parameter constraints
42 * various parameters used to configure a PLL. These limits ensure
43 * the PLL operates within valid and stable ranges.
45 * @fout: Output frequency range (in MHz)
49 * @fvco: PLL oscillation frequency range (in MHz)
53 * @m: Main-divider range
54 * @m.min: Minimum main-divider value
55 * @m.max: Maximum main-divider value
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H A Danalogbits-wrpll-cln28hpc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018-2019 SiFive, Inc.
19 * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
21 * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
22 * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
24 * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
37 * struct wrpll_cfg - WRPLL configuration values
38 * @divr: reference divider value (6 bits), as presented to the PLL signals
39 * @divf: feedback divider value (9 bits), as presented to the PLL signals
40 * @divq: output divider value (3 bits), as presented to the PLL signals
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/linux/drivers/clk/rockchip/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_determine_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_determine_rate()
71 /* Assuming rate_table is in descending order */ in rockchip_pll_determine_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_determine_rate()
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/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
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H A Dmach64_gx.c1 // SPDX-License-Identifier: GPL-2.0
36 #define MAX_N 255-8
60 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); in aty_StrobeClock()
81 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
83 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_dac_514()
124 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
154 pll->ibm514.m = RGB514_clocks[i].m; in aty_var_to_pll_514()
155 pll->ibm514.n = RGB514_clocks[i].n; in aty_var_to_pll_514()
158 return -EINVAL; in aty_var_to_pll_514()
162 const union aty_pll *pll) in aty_pll_514_to_var() argument
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/linux/drivers/clk/samsung/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
14 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
25 /* PLL enable control bit offset in @con_reg register */
27 /* PLL lock status bit offset in @con_reg register */
37 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
39 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
42 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
53 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_determine_rate() local
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/linux/drivers/clk/st/
H A Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20 * Maximum input clock to the PLL before we divide it down by 2
21 * although in reality in actual systems this has never been seen to
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 is controlled by a HW block referred to as a "pad" in the Tegra hardware
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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