Home
last modified time | relevance | path

Searched +full:pci +full:- +full:iommu (Results 1 – 25 of 185) sorted by relevance

12345678

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
29 PCI root complex
33 -------------------
[all …]
H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCI Endpoint Controller
10 Common properties for PCI Endpoint Controller Nodes.
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 iommu-map:
[all …]
H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
25 used to take the PCI devices on those ports out of reset. Therefore
26 the standard "reset-gpios" and "max-link-speed" properties appear on
27 the child nodes that represent the PCI bridges that correspond to
38 - items:
39 - enum:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/virtio/
H A Diommu.txt1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
4 discovered dynamically by the PCI probing infrastructure. However the
5 device tree statically describes the relation between IOMMU and DMA
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
7 contains a child node representing the IOMMU device explicitly.
11 - compatible: Should be "virtio,pci-iommu"
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
13 Binding reference [1], the reg property is a five-cell
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
[all …]
H A Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
14 discovered dynamically by the PCI probing infrastructure. However the
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
[all …]
H A Dmmio.txt3 See https://ozlabs.org/~rusty/virtio-spec/ for more details.
7 - compatible: "virtio,mmio" compatibility string
8 - reg: control registers base address and size including configuration space
9 - interrupts: interrupt generated by the device
11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
21 - iommus: If the device accesses memory through an IOMMU, it should
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <tjeznach@rivosinc.com>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
[all …]
H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
[all …]
/freebsd/sys/conf/
H A Dfiles.x8610 # The long compile-with and dependency lines are required because of
11 # limitations in config: backslash-newline doesn't work in strings, and
16 compile-with "${KEYMAP} -L ${ATKBD_DFLT_KEYMAP} | ${KEYMAP_FIX} > ${.TARGET}" \
17 no-obj no-implicit-rule before-depend \
19 cddl/dev/fbt/x86/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
20 cddl/dev/dtrace/x86/dis_tables.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}"
21 cddl/dev/dtrace/x86/instr_size.c optional dtrace_fbt | dtraceall compile-with "${DTRACE_C}"
25 …compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} -mmmx -msse -m…
26 no-implicit-rule \
30 …compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${NO_WCAST_QUAL} -mmmx -msse -m…
[all …]
H A Dfiles.arm6427 arm64/acpica/pci_cfgreg.c optional acpi pci
63 arm64/arm64/locore.S standard no-obj
76 compile-with "${NORMAL_C:N-mbranch-protection*} -mbranch-protection=bti"
93 compile-with "${NOSAN_C}"
118 arm64/iommu/iommu.c optional iommu
119 arm64/iommu/iommu_if.m optional iommu
120 arm64/iommu/iommu_pmap.c optional iommu
121 arm64/iommu/smmu.c optional iommu
122 arm64/iommu/smmu_acpi.c optional iommu acpi
123 arm64/iommu/smmu_fdt.c optional iommu fdt
[all …]
/freebsd/sys/dev/iommu/
H A Dbusdma_iommu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
59 #include <dev/iommu/iommu.h>
63 #include <machine/iommu.h>
64 #include <dev/iommu/busdma_iommu.h>
68 * IOMMU units from Intel VT-d.
78 static const char iommu_str[] = "iommu"; in iommu_bus_dma_is_dev_disabled()
92 snprintf(str, sizeof(str), "hw.busdma.pci%d.%d.%d.%d", in iommu_bus_dma_is_dev_disabled()
[all …]
/freebsd/sys/amd64/vmm/amd/
H A Damdvi_priv.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 ((1 << (((n) - (m)) + 1)) - 1))
43 * IOMMU PCI capability.
52 * IOMMU extended features.
57 #define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
68 * NOTE: Must be 256-bits/32 bytes aligned.
112 * IOMMU command entry.
127 #define AMDVI_PREFETCH_PAGES_OPCODE 0x6 /* Prefetch IOMMU pages. */
151 * IOMMU event entry.
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
[all …]
/freebsd/sys/arm64/iommu/
H A Diommu_if.m1 #-
2 # SPDX-License-Identifier: BSD-2-Clause
8 # Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 #include <dev/iommu/iommu.h>
52 INTERFACE iommu;
55 # Check if the iommu controller dev is responsible to serve traffic
86 # Allocate an IOMMU domain.
90 struct iommu_unit *iommu;
[all …]
H A Dsmmu_fdt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/iommu/iommu.h>
51 #include <dev/iommu/iommu.h>
53 #include <arm64/iommu/iommu.h>
58 { "arm,smmu-v3", 1 },
68 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in smmu_fdt_probe()
81 struct iommu_unit *iommu; in smmu_fdt_attach() local
[all …]
/freebsd/sys/x86/iommu/
H A Dintel_ctx.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 #include <dev/pci/pcireg.h>
60 #include <dev/pci/pcivar.h>
66 #include <dev/iommu/busdma_iommu.h>
67 #include <x86/iommu/intel_reg.h>
68 #include <x86/iommu/x86_iommu.h>
69 #include <x86/iommu/intel_dmar.h>
90 ctxm = iommu_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_NOALLOC); in dmar_ensure_ctx_page()
101 ctxm = iommu_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_ZERO | in dmar_ensure_ctx_page()
[all …]
H A Dintel_fault.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
55 #include <x86/iommu/intel_reg.h>
56 #include <dev/iommu/busdma_iommu.h>
57 #include <x86/iommu/x86_iommu.h>
58 #include <x86/iommu/intel_dmar.h>
64 * unit->fault_log, and schedules a task.
69 * register file. The task is usually long-running, since printf() is
[all …]
H A Dintel_drv.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
71 #include <dev/iommu/busdma_iommu.h>
72 #include <x86/iommu/intel_reg.h>
73 #include <x86/iommu/x86_iommu.h>
74 #include <x86/iommu/intel_dmar.h>
105 ptrend = (char *)dmartbl + dmartbl->Header.Length; in dmar_iterate_tbl()
[all …]
/freebsd/sys/dev/pci/
H A Dpci_host_generic_fdt.c1 /*-
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcireg.h>
58 #include <dev/pci/pcib_private.h>
59 #include <dev/pci/pci_host_generic.h>
60 #include <dev/pci/pci_host_generic_fdt.h>
95 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { in generic_pcie_fdt_probe()
96 device_set_desc(dev, "Generic PCI host controller"); in generic_pcie_fdt_probe()
116 STAILQ_INIT(&sc->pci_ofw_devlist); in pci_host_generic_setup_fdt()
120 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); in pci_host_generic_setup_fdt()
[all …]

12345678