| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | fsl-enetc.txt | 4 external) there are two supported link modes specified by
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
26 - phy-handle : Phandle to a PHY on the MDIO bus.
29 - phy-connection-type : Defined in ethernet.txt.
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| H A D | fsl,fman-mdio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Frame Manager MDIO Device
10 - Frank Li <Frank.Li@nxp.com>
12 description: FMan MDIO Node.
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
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| H A D | fsl,enetc-mdio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,enetc-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ENETC external MDIO PCIe endpoint device
10 NETC provides an external master MDIO interface (EMDIO) for managing external
12 provides a means for different software modules to share a single set of MDIO
16 - Frank Li <Frank.Li@nxp.com>
17 - Vladimir Oltean <vladimir.oltean@nxp.com>
18 - Wei Fang <wei.fang@nxp.com>
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| H A D | allwinner,sun8i-a83t-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Che
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| H A D | fsl-fman.txt | 5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
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| H A D | xilinx_axienet.txt | 2 --------------------------------------------------------
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
29 - phy-handle : Should point to the external phy device if exists. Pointing
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| H A D | brcm,bcmgenet.txt | 4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or
6 "brcm,bcm7712-genet-v5".
7 - reg: address and length of the register set for the device
8 - interrupts and/or interrupts-extended: must be two cells, the first cell
11 optional third interrupt cell for Wake-on-LAN can be specified.
12 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
14 - phy-mode: see ethernet.txt file in the same directory
15 - #address-cells: should be 1
16 - #size-cells: should be 1
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| H A D | xilinx_gmii2rgmii.txt | 2 --------------------------------------------------------
5 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
8 The Management Data Input/Output (MDIO) interface is used to configure the
10 Different speed modes by configuring the conveter register through mdio write.
12 This converter sits between the ethernet MAC and the external phy.
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Should be "xlnx,gmii-to-rgmii-1.0"
19 - reg : The ID number for the phy, usually a small integer
20 - phy-handle : Should point to the external phy device.
24 mdio {
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| H A D | amlogic,gxl-mdio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic GXL MDIO bus multiplexer
10 - Jerome Brunet <jbrunet@baylibre.com>
13 This is a special case of a MDIO bus multiplexer. It allows to choose between
14 the internal mdio bus leading to the embedded 10/100 PHY or the external
15 MDIO bus on the Amlogic GXL SoC family.
18 - $ref: mdio-mux.yaml#
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| H A D | brcm,bcm6368-mdio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6368 MDIO bus multiplexer
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
14 external to SoCs. When child bus is selected, one needs to select these two
15 properties as well to generate desired MDIO transaction on appropriate bus.
18 - $ref: mdio-mux.yaml#
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| H A D | brcm,mdio-mux-iproc.txt | 1 Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
3 This MDIO bus multiplexer defines buses that could be internal as well as
4 external to SoCs and could accept MDIO transaction compatible to C-22 or
5 C-45 Clause. When child bus is selected, one needs to select these two
6 properties as well to generate desired MDIO transaction on appropriate bus.
10 MDIO multiplexer node:
11 - compatible: brcm,mdio-mux-iproc.
13 Every non-ethernet PHY requires a compatible so that it could be probed based
17 - clocks: phandle of the core clock which drives the mdio block.
20 at- Documentation/devicetree/bindings/net/mdio-mux.yaml
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| H A D | mdio-mux-meson-g12a.txt | 1 Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
3 This is a special case of a MDIO bus multiplexer. It allows to choose between
4 the internal mdio bus leading to the embedded 10/100 PHY or the external
5 MDIO bus.
8 - compatible : amlogic,g12a-mdio-mux
9 - reg: physical address and length of the multiplexer/glue registers
10 - clocks: list of clock phandle, one for each entry clock-names.
11 - clock-names: should contain the following:
18 mdio_mux: mdio-multiplexer@4c000 {
19 compatible = "amlogic,g12a-mdio-mux";
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| H A D | brcm,mdio-mux-iproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer found in Broadcom iProc based SoCs.
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
14 external to SoCs and could accept MDIO transaction compatible to C-22 or
15 C-45 Clause. When child bus is selected, one needs to select these two
16 properties as well to generate desired MDIO transaction on appropriate bus.
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| H A D | qcom,ipq4019-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ40xx MDIO Controller
10 - Robert Marko <robert.marko@sartura.hr>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
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| H A D | amlogic,g12a-mdio-mux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
10 This is a special case of a MDIO bus multiplexer. It allows to choose between
11 the internal mdio bus leading to the embedded 10/100 PHY or the external
12 MDIO bus.
15 - Neil Armstrong <neil.armstrong@linaro.org>
18 - $ref: mdio-mux.yaml#
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | marvell.txt | 2 ----------
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| H A D | lan9303.txt | 2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
38 compatible = "smsc,lan9303-i2c";
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| H A D | qca8k.txt | 5 - compatible: should be one of:
10 - #size-cells: must be 0
11 - #address-cells: must be 1
15 - reset-gpios: GPIO to be used to reset the whole device
20 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
21 mdio-bus each subnode describing a port needs to have a valid phandle
24 To declare the internal mdio-bus configuration, declare a mdio node in the
26 PHY is connected to. In this config a internal mdio-bus is registered and
27 the mdio MASTER is used as communication.
29 Don't use mixed external and internal mdio-bus configurations, as this is
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| H A D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
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| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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| H A D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/dev/dpaa2/ |
| H A D | memac_mdio_common.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2022 Bjoern A. Zeeb
50 /* -------------------------------------------------------------------------- */
70 if (sc->dpnidev != NULL) in memacphy_miibus_statchg()
71 MIIBUS_STATCHG(sc->dpnidev); in memacphy_miibus_statchg()
83 device_printf(sc->dev, "setting nidev %p (%s)\n", in memacphy_set_ni_dev()
87 if (sc->dpnidev != NULL) in memacphy_set_ni_dev()
90 sc->dpnidev = nidev; in memacphy_set_ni_dev()
102 if (sc->phy == -1) { in memacphy_get_phy_loc()
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | cn9130-cf-pro.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 compatible = "solidrun,cn9130-clearfog-pro",
21 "solidrun,cn9130-sr-som", "marvell,cn9130";
23 gpio-keys {
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-381-netgear-gs110emx.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 /dts-v1/;
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
14 /* So that mvebu u-boo
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| /freebsd/sys/contrib/device-tree/src/mips/loongson/ |
| H A D | loongson64-2k1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
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