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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // RISC-V subtarget features and instruction predicates.
11 //===----------------------------------------------------------------------===//
13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V
16 // name - Name of the extension in lower case.
17 // major - Major version of extension.
18 // minor - Minor version of extension.
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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp1 //===- LowerMatrixIntrinsics.cpp - Lower matrix intrinsics -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Lower matrix intrinsics to vector operations.
13 // * Support more cases, e.g. multiply-add, multiply-sub, operands/results
15 // * Improve cost-modeling, e.g. choose different number of rows/columns
18 //===----------------------------------------------------------------------===//
53 #define DEBUG_TYPE "lower-matrix-intrinsics"
56 FuseMatrix("fuse-matrix", cl::init(true), cl::Hidden,
57 cl::desc("Enable/disable fusing matrix instructions."));
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td1 //=- AArch64Features.td - Describe AArch64 SubtargetFeatures -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
17 string TargetFeatureName, // String used for -target-feature, unless overridden.
28 // The user visible name used by -march/-mcpu modifiers and target attribute
37 // An Extension that can be toggled via a '-march'/'-mcpu' modifier or a target
40 …string TargetFeatureName, // String used for -target-feature and -march, unless overrid…
47 // used for -target-feature. However, there are exceptions. Therefore we
62 //===----------------------------------------------------------------------===//
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H A DAArch64SchedNeoverseV1.td1 //=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // - "Arm Neoverse V1 Software Optimization Guide"
13 // - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing"
14 …//community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-plat…
15 // - "Neoverse V1"
19 //===----------------------------------------------------------------------===//
22 let IssueWidth = 15; // Maximum micro-ops dispatch rate.
23 let MicroOpBufferSize = 256; // Micro-op re-order buffer.
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H A DAArch64SchedNeoverseV2.td1 //=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2
14 //===----------------------------------------------------------------------===//
17 let IssueWidth = 16; // Micro-ops dispatched at a time.
18 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
29 //===----------------------------------------------------------------------===//
31 // Instructions are first fetched and then decoded into internal macro-ops
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H A DAArch64SchedA510.td1 //==- AArch64SchedCortexA510.td - ARM Cortex-A510 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the ARM Cortex-A510 processor.
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // The following definitions describe the per-operand machine model.
17 // Cortex-A510 machine model for scheduling and other instruction cost heuristics.
19 let MicroOpBufferSize = 0; // The Cortex-A510 is an in-order processor
20 let IssueWidth = 3; // It dual-issues under most circumstances
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H A DAArch64SchedNeoverseN2.td1 //=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 10; // Micro-ops dispatched at a time.
15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
25 //===----------------------------------------------------------------------===//
27 // Instructions are first fetched and then decoded into internal macro-ops
29 // stages. A MOP can be split into two micro-ops further down the pipeline
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H A DAArch64SchedAmpere1B.td1 //=- AArch64SchedAmpere1B.td - Ampere-1B scheduling def -----*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the Ampere Computing Ampere-1B to
10 // support instruction scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 // The Ampere-1B core is an out-of-order micro-architecture. The front
15 // end has branch prediction, with a 10-cycle recovery time from a
17 // decoded into internal micro-ops (uops).
20 let IssueWidth = 12; // Maximum micro-ops dispatch rate.
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H A DAArch64SchedAmpere1.td1 //=- AArch64SchedAmpere1.td - Ampere-1 scheduling def -----*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the Ampere Computing Ampere-1 to
10 // support instruction scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 // The Ampere-1 core is an out-of-order micro-architecture. The front
15 // end has branch prediction, with a 10-cycle recovery time from a
17 // decoded into internal micro-ops (uops).
20 let IssueWidth = 4; // 4-way decode and dispatch
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H A DSVEInstrFormats.td1 //=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
11 //===----------------------------------------------------------------------===//
14 // Non-matches return VT, which often means VT is the container type.
52 return N->hasOneUse();
342 return N->hasOneUse();
347 return N->hasOneUse();
351 //===----------------------------------------------------------------------===//
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H A DAArch64InstrFormats.td1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
13 // Format specifies the encoding used by the instruction. This is part of the
14 // ad-hoc solution used to emit machine instruction encodings by our machine
23 // Enum describing whether an instruction is
59 // AArch64 Instruction Format
60 class AArch64Inst<Format f, string cstr> : Instruction {
61 field bits<32> Inst; // Instruction encoding.
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H A DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // AArch64 Instruction definitions.
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
21 def HasV8_0a : Predicate<"Subtarget->hasV8_0aOps()">,
23 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
25 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
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/freebsd/sys/libkern/x86/
H A Dcrc32_sse42.c6 * This software is provided 'as-is', without any express or implied warranty.
43 * clang (at least 3.9.[0-1]) pessimizes "rm" (y) and "m" (y) in _mm_crc32_u8()
46 * the latter. This costs a register and an instruction but in _mm_crc32_u8()
69 /* CRC-32C (iSCSI) polynomial in reversed bit order. */
73 * Block sizes for three-way parallel crc computation. LONG and SHORT must
90 * Multiply a matrix times a vector over the Galois field of two elements,
111 * Multiply a matrix by itself over GF(2). Both mat and square must have 32
133 uint32_t odd[32]; /* odd-power-of-two zeros operator */ in crc32c_zeros_op()
138 odd[0] = POLY; /* CRC-32C polynomial */ in crc32c_zeros_op()
153 * bits), in even -- next square puts operator for two zero bytes in in crc32c_zeros_op()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td1 //===----------------------------------------------------------------------===//
6 def ModeThumb : SubtargetFeature<"thumb-mode", "IsThumb",
10 def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
14 //===----------------------------------------------------------------------===//
21 string TargetFeatureName, // String used for -target-feature.
32 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
38 // extension) and MVE (even in the integer-only version).
40 "Enable 16-bit FP registers",
44 "Enable 64-bit FP registers",
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H A DARMInstrNEON.td1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the ARM NEON instruction set.
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
266 // ...with half-word lane subscripting.
297 // ...with half-word lane subscripting.
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the AARCH64-specific intrinsics.
11 //===----------------------------------------------------------------------===//
61 //===----------------------------------------------------------------------===//
79 //===----------------------------------------------------------------------===//
89 // A space-consuming intrinsic primarily for testing block and jump table
90 // placements. The first argument is the number of bytes this "instruction"
95 //===----------------------------------------------------------------------===//
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H A DIntrinsicsAMDGPU.td1 //===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the R600-specific intrinsics.
11 //===----------------------------------------------------------------------===//
15 // The amdgpu-no-* attributes (ex amdgpu-no-workitem-id-z) typically inferred
16 // by the backend cause whole-program undefined behavior when violated, such as
18 // values. In non-entry-point functions, attempting to call a function that needs
20 // of the calling convention and also program-level UB. Outside of such IR-level UB,
21 // these preloaded registers are always set to a well-defined value and are thus `noundef`.
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H A DIntrinsicsARM.td1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the ARM-specific intrinsics.
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
19 // A space-consuming intrinsic primarily for testing ARMConstantIslands. The
20 // first argument is the number of bytes this "instruction" takes up, the second
24 // 16-bit multiplications
44 //===----------------------------------------------------------------------===//
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/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.in2 %%% BibTeX-file{
23 %%% (incompletely) 1970 -- 1979.
50 %%% covering 1958--1996 became too large (about
65 %%% Algorithms 1--492. For Algorithms 493--686,
72 %%% cross-referenced in both directions, so
75 %%% Corrigenda. Cross-referenced entries are
77 %%% that each is completely self-contained.
83 %%% ftp://netlib.bell-labs.com/netlib/toms.
88 %%% http://ciir.cs.umass.edu/cgi-bin/web_query_form/public/cacm2.1.
90 %%% The initial draft of entries for 1981 --
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "x86-isel"
74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
78 "alignment set by x86-experimental-pref-loop-alignment."),
82 "x86-br-merging-base-cost", cl::init(2),
87 "This value sets the instruction cost limit, below which conditionals "
88 "will be merged, and above which conditionals will be split. Set to -1 "
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp1 //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
93 I->addAnnotationMetadata("auto-init"); in initializeAlloca()
96 /// getBuiltinLibFunction - Given a builtin id for a function like
106 // TODO: This list should be expanded or refactored after all GCC-compatible in getBuiltinLibFunction()
134 // The AIX library functions frexpl, ldexpl, and modfl are for 128-bit in getBuiltinLibFunction()
136 // if it is 64-bit 'long double' mode. in getBuiltinLibFunction()
146 if (FD->hasAttr<AsmLabelAttr>()) in getBuiltinLibFunction()
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/freebsd/contrib/sqlite3/
H A Dsqlite3.c17 ** language. The code for the "sqlite3" command-line shell is also in a
20 ** The content in this amalgamation comes from Fossil check-in
54 ** NO_TEST - The branches on this line are not
59 ** OPTIMIZATION-IF-TRUE - This branch is allowed to always be false
63 ** OPTIMIZATION-IF-FALSE - This branch is allowed to always be true
67 ** PREVENTS-HARMLESS-OVERREAD - This branch prevents a buffer overread
72 ** slash-asterisk...asterisk-slash comment marks, with no spaces between the
147 ** 2015-03-02
185 ** large file support, or if the OS is windows, these should be no-ops.
191 ** Large file support can be disabled using the -DSQLITE_DISABLE_LFS switch
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/freebsd/share/dict/
H A Dweb21063 accumulate
95602 instruction
99810 Jean-Christophe
99811 Jean-Pierre
112430 matrix
120735 multiply