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Searched +full:keystone +full:- +full:dsp +full:- +full:gpio (Results 1 – 14 of 14) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking soc specific device tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
11 compatible = "ti,k2hk", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Kepler/Hawking SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
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H A Dkeystone-k2l.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Lamarr SoC specific device tree
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
11 compatible = "ti,k2l", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Lamarr SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
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H A Dkeystone-k2e.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Edison soc device tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
11 compatible = "ti,k2e", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Edison SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
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H A Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
13 compatible = "ti,k2g","ti,keystone";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
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H A Dkeystone-k2hk-evm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking EVM device tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone.dtsi"
10 #include "keystone-k2hk.dtsi"
13 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
14 model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
16 reserved-memory {
17 #address-cells = <2>;
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H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 dsp_common_memory: dsp-common-memory@81f800000 {
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dti,keystone-dsp-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 DSP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 HOST OS userland running on ARM can send interrupts to DSP cores using
14 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
15 This is one of the component used by the IPC mechanism used on Keystone SOCs.
17 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
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H A Dgpio-dsp-keystone.txt1 Keystone 2 DSP GPIO controller bindings
3 HOST OS userland running on ARM can send interrupts to DSP cores using
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
5 This is one of the component used by the IPC mechanism used on Keystone SOCs.
7 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
8 - 8 for C66x CorePacx CPUs 0-7
10 Keystone 2 DSP GPIO controller has specific features:
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,keystone-rproc.txt1 TI Keystone DSP devices
4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
13 DSP Device Node:
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j784s4-j742s2-main-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
29 compatible = "mmio-sram";
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
24 #address-cells = <2>;
25 #size-cells = <2>;
27 #interrupt-cells = <3>;
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2025-10-18 03:15:01
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
51 7a19 PCI-to-PCI Bridge
57 7a29 PCI-to-PCI Bridge
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