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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-core-clock.txt1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
[all …]
H A Dst,stm32mp25-rcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32MP25 Reset Clock Controller
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
13 The RCC hardware block is both a reset and a clock controller.
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
[all …]
H A Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dk210-fpioa.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
14 #define K210_PCF_JTAG_TCLK 0 /* JTAG Test Clock */
31 #define K210_PCF_SPI0_SCLK 17 /* SPI0 Serial Clock */
36 #define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */
37 #define K210_PCF_CLK_I2C1 23 /* Clock I2C1 */
97 #define K210_PCF_SPI1_SCLK 83 /* SPI1 Serial Clock */
100 #define K210_PCF_SPI2_SCLK 86 /* SPI2 Serial Clock */
101 #define K210_PCF_I2S0_MCLK 87 /* I2S0 Master Clock */
102 #define K210_PCF_I2S0_SCLK 88 /* I2S0 Serial Clock(BCLK) */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Damlogic,meson-gx.txt10 - compatible : contains one of:
11 - "amlogic,meson-gx-mmc"
12 - "amlogic,meson-gxbb-mmc"
13 - "amlogic,meson-gxl-mmc"
14 - "amlogic,meson-gxm-mmc"
15 - "amlogic,meson-axg-mmc"
16 - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
17 - clock-names: Should contain the following:
18 "core" - Main peripheral bus clock
19 "clkin0" - Parent clock of internal mux
[all …]
H A Dmtk-sd.txt10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
18 "mediatek,mt7622-mmc": for MT7622 SoC
19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
[all …]
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbi
[all...]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylweste
[all...]
H A Dnvidia,tegra-audio-rt5677.txt4 - compatible : "nvidia,tegra-audio-rt5677"
5 - clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
7 - clock-names : Must include the following entries:
8 - pll_a
9 - pll_a_out0
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
21 * Internal Mic 1
[all …]
H A Dmvebu-audio.txt5 - compatible:
6 "marvell,kirkwood-audio" for Kirkwood platforms
7 "marvell,dove-audio" for Dove platforms
8 "marvell,armada370-audio" for Armada 370 platforms
9 "marvell,armada-380-audio" for Armada 38x platforms
11 - reg: physical base address of the controller and length of memory mapped
13 With "marvell,armada-380-audio" two other regions are required:
15 (named "pll_regs") and the second one ("soc_ctrl") - for register
18 - interrupts:
19 with "marvell,kirkwood-audio", the audio interrupt
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
H A Daspeed,ast2600-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Billy Tsai <billy_tsai@aspeedtech.com>
13 • 10-bits resolution for 16 voltage channels.
16 • Channel scanning can be non-continuous.
17 • Programmable ADC clock frequency.
21 • Built-in a compensating method.
22 • Built-in a register to trim internal reference voltage.
[all …]
H A Dti,ads131e08.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
10 - Jonathan Cameron <jic23@kernel.org>
14 24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
15 built-in programmable gain amplifier (PGA), internal reference
24 - ti,ads131e04
25 - ti,ads131e06
26 - ti,ads131e08
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drenesas,drif.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
[all …]
H A Drenesas,drif.txt1 Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
2 ------------------------------------------------------------
4 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
7 +---------------------+ +---------------------+
8 | |-----SCK------->|CLK |
9 | Master |-----SS-------->|SYNC DRIFn (slave) |
10 | |-----SD0------->|D0 |
11 | |-----SD1------->|D1 |
12 +---------------------+ +---------------------+
14 As per datasheet, each DRIF channel (drifn) is made up of two internal
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/imu/
H A Dadi,adis16480.txt6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dnetwork.txt4 - fsl,cpm1-scc-enet
5 - fsl,cpm2-scc-enet
6 - fsl,cpm1-fec-enet
7 - fsl,cpm2-fcc-enet (third resource is GFEMR)
8 - fsl,qe-enet
13 compatible = "fsl,mpc8272-fcc-enet",
14 "fsl,cpm2-fcc-enet";
16 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupt-parent = <&PIC>;
19 phy-handle = <&PHY0>;
[all …]

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