Searched +full:gs101 +full:- +full:cmu +full:- +full:top (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Google GS101 SoC clock controller10 - Peter Griffin <peter.griffin@linaro.org>13 Google GS101 clock controller is comprised of several CMU units, generating14 clocks for different domains. Those CMU units are modeled as separate device16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst37 F: */net/* all files in "any top level directory"/net46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org[all …]