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Searched +full:fw +full:- +full:cfg +full:- +full:mmio (Results 1 – 20 of 20) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dqemu,fw-cfg-mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/firmware/qemu,fw-cfg-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - A write-only, 16-bit wide selector (or control) register,
17 - a read-write, 64-bit wide data register.
23 The authoritative guest-side hardware interface documentation to the fw_cfg
29 const: qemu,fw-cfg-mmio
39 dma-coherent: true
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dfw-cfg.txt3 QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
7 - A write-only, 16-bit wide selector (or control) register,
8 - a read-write, 64-bit wide data register.
14 The authoritative guest-side hardware interface documentation to the fw_cfg
20 - compatible: "qemu,fw-cfg-mmio".
22 - reg: the MMIO region used by the device.
31 #size-cells = <0x2>;
32 #address-cells = <0x2>;
34 fw-cfg@9020000 {
35 compatible = "qemu,fw-cfg-mmio";
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am65-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 cpsw_mac_syscon: ethernet-mac-syscon@200 {
16 compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
21 compatible = "ti,am654-phy-gmii-sel";
23 #phy-cells = <1>;
29 compatible = "pinctrl-single";
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j784s4-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 bootph-all;
11 compatible = "ti,k2g-sci";
12 ti,host-id = <12>;
14 mbox-names = "rx", "tx";
19 reg-names = "debug_messages";
22 k3_pds: power-controller {
23 bootph-all;
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H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam4372.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/am4.h>
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
41 #address-cells = <1>;
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac_mcu.c1 // SPDX-License-Identifier: ISC
107 struct mt76_dev *dev = phy->dev; in mt76_connac_mcu_set_channel_domain()
111 n_max_channels = phy->sband_2g.sband.n_channels + in mt76_connac_mcu_set_channel_domain()
112 phy->sband_5g.sband.n_channels + in mt76_connac_mcu_set_channel_domain()
113 phy->sband_6g.sband.n_channels; in mt76_connac_mcu_set_channel_domain()
118 return -ENOMEM; in mt76_connac_mcu_set_channel_domain()
122 for (i = 0; i < phy->sband_2g.sband.n_channels; i++) { in mt76_connac_mcu_set_channel_domain()
123 chan = &phy->sband_2g.sband.channels[i]; in mt76_connac_mcu_set_channel_domain()
124 if (chan->flags & IEEE80211_CHAN_DISABLED) in mt76_connac_mcu_set_channel_domain()
127 channel.hw_value = cpu_to_le16(chan->hw_value); in mt76_connac_mcu_set_channel_domain()
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/freebsd/sys/dev/liquidio/
H A Dlio_main.c213 while (tbl->vendor_id) { in lio_probe()
214 if ((vendor_id == tbl->vendor_id) && in lio_probe()
215 (device_id == tbl->device_id) && in lio_probe()
216 (subdevice_id == tbl->subdevice_id) && in lio_probe()
217 (revision_id == tbl->revision_id)) { in lio_probe()
218 device_set_descf(dev, "%s, Version - %s", in lio_probe()
219 lio_strings[tbl->index], LIO_VERSION); in lio_probe()
241 return (-ENOMEM); in lio_attach()
244 oct_dev->tx_budget = LIO_DEFAULT_TX_PKTS_PROCESS_BUDGET; in lio_attach()
245 oct_dev->rx_budget = LIO_DEFAULT_RX_PKTS_PROCESS_BUDGET; in lio_attach()
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
132 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
146 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
163 return self ? hweight32(self->accel_mask) : 0; in get_num_accels()
169 return self ? hweight32(self->ae_mask) : 0; in get_num_aes()
198 * c4xxx_set_ssm_wdtimer() - Initialize the slice hang watchdog timer.
206 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in c4xxx_set_ssm_wdtimer()
208 &GET_BARS(accel_dev)[hw_device->get_misc_bar_id(hw_device)]; in c4xxx_set_ssm_wdtimer()
209 struct resource *csr = misc_bar->virt_addr; in c4xxx_set_ssm_wdtimer()
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
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H A Dsa8775p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/power/qcom,rpmhpd.h>
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/freebsd/sys/dev/bnxt/bnxt_en/
H A Dhsi_struct_def.h1 /*-
34 * Copyright(c) 2001-2025, Broadcom. All rights reserved. The
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
122 /* Engine CKV - The Alias key EC curve and ECC public key information. */
124 /* Engine CKV - Initialization vector. */
126 /* Engine CKV - Authentication tag. */
128 /* Engine CKV - The encrypted data. */
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