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/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
[all …]
H A Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
H A Dcirrus,ep9301-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cirrus,ep9301-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: ethernet-controller.yaml#
19 - const: cirrus,ep9301-eth
20 - items:
21 - enum:
[all …]
H A Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
[all …]
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
H A Dmarvell-pxa168.txt4 - compatible: should be "marvell,pxa168-eth".
5 - reg: address and length of the register set for the device.
6 - interrupts: interrupt for the device.
7 - clocks: pointer to the clock for the device.
10 - port-id: Ethernet port number. Should be '0','1' or '2'.
11 - #address-cells: must be 1 when using sub-nodes.
12 - #size-cells: must be 0 when using sub-nodes.
13 - phy-handle: see ethernet.txt file in the same directory.
18 Sub-nodes:
19 Each PHY can be represented as a sub-node. This is not mandatory.
[all …]
H A Dactions,owl-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
15 IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
19 - $ref: ethernet-controller.yaml#
24 - const: actions,owl-emac
25 - items:
26 - enum:
[all …]
H A Dnxp,lpc-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,lpc-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
14 const: nxp,lpc-eth
25 use-iram:
30 - compatible
31 - reg
32 - interrupts
[all …]
/linux/arch/mips/cavium-octeon/
H A Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
19 #include <asm/octeon/cvmx-helper-board.h>
25 #include <asm/octeon/cvmx-uctlx-defs.h>
79 if (dev->of_node) { in octeon2_usb_clocks_start()
83 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
89 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
91 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
96 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
123 /* Step 3: Configure the reference clock, PHY, and HCLK */ in octeon2_usb_clocks_start()
204 * Step 4: Program the power-on reset field in the UCTL in octeon2_usb_clocks_start()
[all …]
/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Dmac-phy-support.rst1 .. SPDX-License-Identifier: GPL-2.0
5 DPAA2 MAC / PHY support
11 --------
13 The DPAA2 MAC / PHY support consists of a set of APIs that help DPAA2 network
14 drivers (dpaa2-eth, dpaa2-ethsw) interact with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
26 directly by the dpaa2-eth driver or by phylink.
28 .. code-block:: none
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
44 reg_3p3v: regulator-3p3v {
[all …]
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/linux/arch/arm64/boot/dts/ti/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
6 # Copyright (C) 2016-2021 Texas Instruments Incorporated - https://www.ti.com/
12 dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb
13 dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo
14 dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo
15 dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb
16 dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
17 dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb
18 dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb
19 dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb
[all …]
H A Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-fastrhino-r68s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986b-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
33 &eth {
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
41 fixed-link {
43 full-duplex;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <0>;
22 clock-names = "cpu_clk", "ddrclk", "powersave";
33 compatible = "marvell,kirkwood-mbus", "simple-bus";
[all …]
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 /dts-v1/;
9 #include "uniphier-ld11.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
15 compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
18 stdout-path = "serial0:115200n8";
32 ethernet0 = &eth;
54 xirq0-hog {
55 gpio-hog;
[all …]
H A Duniphier-ld20-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld20.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
15 compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
18 stdout-path = "serial0:115200n8";
32 ethernet0 = &eth;
54 xirq0-hog {
[all …]
/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4-sanji.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 /dts-v1/;
9 #include "uniphier-pro4.dtsi"
13 compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
16 stdout-path = "serial0:115200n8";
28 ethernet0 = &eth;
79 &eth {
81 phy-handle = <&ethphy>;
85 ethphy: ethernet-phy@1 {
H A Duniphier-pro4-ace.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 /dts-v1/;
9 #include "uniphier-pro4.dtsi"
13 compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
16 stdout-path = "serial0:115200n8";
29 ethernet0 = &eth;
84 &eth {
86 phy-handle = <&ethphy>;
90 ethphy: ethernet-phy@1 {
H A Duniphier-ld6b-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld6b.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
15 compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
18 stdout-path = "serial0:115200n8";
33 ethernet0 = &eth;
63 xirq4-hog {
[all …]
H A Duniphier-pxs2-gentil.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-pxs2.dtsi"
13 compatible = "socionext,uniphier-pxs2-gentil",
14 "socionext,uniphier-pxs2";
17 stdout-path = "serial0:115200n8";
29 ethernet0 = &eth;
38 compatible = "audio-graph-card";
59 dai-format = "i2s";
[all …]
H A Duniphier-pro4-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-pro4.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
15 compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
18 stdout-path = "serial0:115200n8";
32 ethernet0 = &eth;
62 xirq2-hog {
[all …]

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