Home
last modified time | relevance | path

Searched +full:di0 +full:- +full:3 (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/pwm/
H A Dnxp,mc33xs2410.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-side switch MC33XS2410
10 - Dimitri Fedrau <dima.fedrau@gmail.com>
13 - $ref: pwm.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 spi-max-frequency:
26 spi-cpha: true
28 spi-cs-setup-delay-ns:
[all …]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx6q-ipu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,imx51-ipu
17 - fsl,imx53-ipu
18 - fsl,imx6q-ipu
19 - items:
[all …]
H A Dfsl,imx6q-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The LVDS Display Bridge device tree node contains up to two lvds-channel
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,imx53-ldb
21 - items:
22 - enum:
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx53.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx53-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
[all …]
H A Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx51.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx51-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
42 tzic: tz-interrupt-controller@e0000000 {
[all …]
H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
[all …]
/linux/drivers/pinctrl/berlin/
H A Dpinctrl-as370.c1 // SPDX-License-Identifier: GPL-2.0
33 BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 3P3V RSTB */
64 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */
93 BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI0 */
326 .compatible = "syna,as370-soc-pinctrl",
335 device_get_match_data(&pdev->dev); in as370_pinctrl_probe()
341 rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); in as370_pinctrl_probe()
343 return -ENOMEM; in as370_pinctrl_probe()
349 rmconfig->reg_bits = 32, in as370_pinctrl_probe()
350 rmconfig->val_bits = 32, in as370_pinctrl_probe()
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun50i-h616.c1 // SPDX-License-Identifier: GPL-2.0
15 #include "pinctrl-sunxi.h"
37 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
118 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PC_EINT3 */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
226 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PD_EINT3 */
388 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PE_EINT0 */
393 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PE_EINT1 */
[all …]
H A Dpinctrl-sun8i-a83t.c6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
42 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
46 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
47 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
186 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
240 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
[all …]
H A Dpinctrl-sun50i-a64.c4 * Copyright (C) 2016 - ARM Ltd.
7 * Based on pinctrl-sun7i-a20.c, which is:
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include "pinctrl-sunxi.h"
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
48 SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */
50 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
[all …]
/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX drm driver - LVDS display bridge
11 #include <linux/media-bus-format.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
33 #include "imx-drm.h"
35 #define DRIVER_NAME "imx-ld
[all...]
/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
48 DI_PIN14 = 3,
62 DI_SYNC_HSYNC = 3,
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
92 #define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3)
[all …]
H A Dipu-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
41 return ipu->id; in ipu_get_num()
157 return -EINVAL; in ipu_degrees_to_rot_mode()
172 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
175 return ERR_PTR(-ENODEV); in ipu_idmac_get()
[all …]
/linux/drivers/comedi/drivers/
H A Dquatech_daqp_cs.c1 // SPDX-License-Identifier: GPL-2.0
8 * COMEDI - Linux Control and Measurement Device Interface
13 * ftp://ftp.quatech.com/Manuals/daqp-208.pdf
15 * This manual is for both the DAQP-208 and the DAQP-308.
18 * - A/D conversion
19 * - 8 channels
20 * - 4 gain ranges
21 * - ground ref or differential
22 * - single-shot and timed both supported
23 * - D/A conversion, single-shot
[all …]
H A Dadv_pci_dio.c1 // SPDX-License-Identifier: GPL-2.0
13 * Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
14 * PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
15 * PCI-1751, PCI-1752, PCI-1753, PCI-1753+PCI-1753E,
16 * PCI-1754, PCI-1756, PCI-1761, PCI-1762
34 /* PCI-1730, PCI-1733, PCI-1736 interrupt control registers */
42 #define PCI173X_INT_DI0 0x04 /* DI0 edge occurred */
45 /* PCI-1739U, PCI-1750, PCI1751 interrupt control registers */
48 /* PCI-1753, PCI-1753E interrupt control registers */
49 #define PCI1753_INT_REG(x) (0x10 + (x)) /* R/W: control group 0 to 3 */
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_lcn.c1 // SPDX-License-Identifier: ISC
44 #define PAPD_BLANKING_PROFILE 3
90 (pi->temppwrctrl_capable)
92 (pi->hwpwrctrl_capable)
126 #define LCNPHY_ACI_DETECT_STOP 3
138 wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + \
222 ((3 << 8) | 0),
230 ((16 << 8) | 3),
258 ((64 << 8) | 3),
272 {-17, 86},
[all …]