/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | marvell,dove-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,dove-pinctrl" 8 - clocks: (optional) phandle of pdma clock 9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers 11 Available mpp pins/groups and functions: 16 name pins functions 19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu* 23 uart1(cts), lcd-spi(cs1), pmu* 25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu* 31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), [all …]
|
H A D | marvell,kirkwood-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,88f6180-pinctrl", 8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", 9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl", 10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl" 11 - reg: register specifier of MPP registers 14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. 16 Available mpp pins/groups and functions: 22 name pins functions 34 mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), [all …]
|
H A D | marvell,armada-370-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,88f6710-pinctrl" 8 - reg: register specifier of MPP registers 10 Available mpp pins/groups and functions: 14 name pins functions 20 mpp4 4 gpio, vdd(cpu-pd) 26 mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) 48 mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts) 59 mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) 73 mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso), [all …]
|
H A D | marvell,armada-xp-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", 8 "marvell,mv78460-pinctrl" 9 - reg: register specifier of MPP registers 13 Available mpp pins/groups and functions: 19 name pins functions 50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) 61 mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), 63 mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), 65 mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) [all …]
|
H A D | marvell,armada-38x-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or 8 "marvell,88f6828-pinctrl" depending on the specific variant of the 10 - reg: register specifier of MPP registers 12 Available mpp pins/groups and functions: 16 name pins functions 23 mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts) 37 mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) 42 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) 57 mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) [all …]
|
H A D | marvell,armada-39x-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or 8 "marvell,88f6928-pinctrl" depending on the specific variant of the 10 - reg: register specifier of MPP registers 12 Available mpp pins/groups and functions: 16 name pins functions 23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio) 37 mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) 43 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) 58 mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) [all …]
|
H A D | img,pistachio-pinctrl.txt | 6 controller on Pistachio has 99 pins, 90 of which are MFIOs which can be 8 each. The GPIO banks are represented as sub-nodes of the pad controller node. 10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and 11 ../interrupt-controller/interrupts.txt for generic information regarding 15 -------------------------------------------- 16 - compatible: "img,pistachio-system-pinctrl". 17 - reg: Address range of the pinctrl registers. 19 Required properties for GPIO bank sub-nodes: 20 -------------------------------------------- 21 - interrupts: Interrupt line for the GPIO bank. [all …]
|
H A D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is: 10 - reg: Should contain the physical address and length of the gpio/pinmux 13 Please refer to pinctrl-bindings.txt in this directory for details of the 19 pin, a group, or a list of pins or groups. This configuration can include the 21 pull-up and open-drain 36 Required subnode-properties: 37 - lantiq,groups : An array of strings. Each string contains the name of a group. 39 - lantiq,function: A string containing the name of the function to mux to the 57 spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, 69 spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, [all …]
|
H A D | marvell,orion-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 7 - compatible: "marvell,88f5181-pinctrl", 8 "marvell,88f5181l-pinctrl", 9 "marvell,88f5182-pinctrl", 10 "marvell,88f5281-pinctrl" 12 - reg: two register areas, the first one describing the first two 16 Available mpp pins/groups and functions: 22 name pins functions 26 mpp2 2 gpio, pci(req3), pci-1(pme) 30 mpp6 6 gpio, pci(req5), pci-1(clk) [all …]
|
/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6qdl-dhcom-drc02.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 8 stdout-path = "serial0:115200n8"; 13 * Special SoM hardware required which uses the pins from micro SD card. The 14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD 16 * card must be disabled and the uart1 rts/cts must be output on other DHCOM 17 * pins, see uart1 and usdhc3 node below. 30 rs485-rx-en-hog { 31 gpio-hog; 33 line-name = "rs485-rx-en"; [all …]
|
H A D | imx6ull-dhcom-drc02.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 6 * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 7 * DHCOR PCB number: 578-200 or newer 8 * DHCOM PCB number: 579-200 or newer 9 * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM) 11 /dts-v1/; 13 #include "imx6ull-dhcom-som.dtsi" 14 #include "imx6ull-dhcom-som-cfg-sdcard.dtsi" 18 compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som", 19 "dh,imx6ull-dhcor-som", "fsl,imx6ull"; [all …]
|
/linux/Documentation/devicetree/bindings/serial/ |
H A D | st,stm32-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 - Erwan Le Ray <erwan.leray@foss.st.com> 15 - st,stm32-uart 16 - st,stm32f7-uart 17 - st,stm32h7-uart 34 st,hw-flow-ctrl: 38 rx-tx-swap: true [all …]
|
/linux/arch/arm/boot/dts/st/ |
H A D | ste-dbx5x0-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include "ste-nomadik-pinctrl.dtsi" 17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 21 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ 28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 32 pins = "GPIO1_AJ3"; /* RTS */ 36 pins = "GPIO3_AH3"; /* TXD */ 49 pins = "GPIO4_AH6"; /* RXD */ 53 pins = "GPIO5_AG6"; /* TXD */ 60 pins = "GPIO4_AH6"; /* RXD */ [all …]
|
/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt8192-asurada-hayato-r1.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 /dts-v1/; 6 #include "mt8192-asurada.dtsi" 10 chassis-type = "convertible"; 11 compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; 15 function-row-physmap = < 44 bt_pins: bt-pins { 45 pins-bt-kill { 47 output-low; 50 pins-bt-wake { [all …]
|
/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mq-hummingboard-pulse.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com> 6 /dts-v1/; 8 #include "dt-bindings/usb/pd.h" 9 #include "imx8mq-sr-som.dtsi" 13 compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq"; 16 stdout-path = &uart1; 19 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 20 compatible = "regulator-fixed"; 21 pinctrl-names = "default"; [all …]
|
/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am335x-netcom-plus-2xx.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 11 /dts-v1/; 13 #include "am335x-baltos.dtsi" 14 #include "am335x-baltos-leds.dtsi" 21 uart1_pins: uart1-pins { 22 pinctrl-single,pins = < 25 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ 34 uart2_pins: uart2-pins { 35 pinctrl-single,pins = < [all …]
|
H A D | motorola-mapphone-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 6 #include "motorola-cpcap-mapphone.dtsi" 10 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked, 11 * then 1023 - 1024 seems to contain mbm. 19 gpio-poweroff { 20 compatible = "gpio-poweroff"; 21 pinctrl-0 = <&poweroff_gpio>; 22 pinctrl-names = "default"; [all …]
|
/linux/drivers/pinctrl/ |
H A D | pinctrl-artpec6.c | 2 * Driver for the Axis ARTPEC-6 pin controller 18 #include <linux/pinctrl/pinconf-generic.h> 24 #include "pinctrl-utils.h" 26 #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */ 59 struct pinctrl_pin_desc *pins; member 69 const unsigned int *pins; member 80 /* pins */ 215 .pins = cpuclkout_pins0, 221 .pins = udlclkout_pins0, 227 .pins = i2c1_pins0, [all …]
|
/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3188.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3188-cru.h> 10 #include <dt-bindings/power/rk3188-power.h> 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; [all …]
|
H A D | rk3066a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/pinctrl/rockchip.h> 9 #include <dt-bindings/clock/rk3066a-cru.h> 10 #include <dt-bindings/power/rk3066-power.h> 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "rockchip,rk3066-smp"; 28 compatible = "arm,cortex-a9"; 29 next-level-cache = <&L2>; [all …]
|
/linux/arch/mips/boot/dts/img/ |
H A D | pistachio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/pistachio-clk.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/mips-gic.h> 11 #include <dt-bindings/reset/pistachio-resets.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 19 interrupt-parent = <&gic>; 22 #address-cells = <1>; [all …]
|
/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc7180-idp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 8 /dts-v1/; 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 14 #include "sc7180-firmware-tfa.dtsi" 20 compatible = "qcom,sc7180-idp", "qcom,sc7180"; 30 stdout-path = "serial0:115200n8"; 42 /delete-node/ &hyp_mem; 43 /delete-node/ &xbl_mem; [all …]
|
H A D | sc7280-qcard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> 15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> 16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 34 wcd9385: audio-codec-1 { 35 compatible = "qcom,wcd9385-codec"; 36 pinctrl-names = "default", "sleep"; 37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; 38 pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>; [all …]
|
/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm2711.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/soc/bcm2835-pm.h> 10 #address-cells = <2>; 11 #size-cells = <1>; 13 interrupt-parent = <&gicv2>; 16 compatible = "brcm,bcm2711-vc5"; 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; [all …]
|
/linux/Documentation/devicetree/bindings/arm/marvell/ |
H A D | cp110-system-controller.txt | 6 giving access to numerous features: clocks, pin-muxing and many other 11 - compatible: must be: "syscon", "simple-mfd"; 12 - reg: register area of the CP110 system controller 18 ------- 23 - a set of core clocks 24 - a set of gateable clocks 28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the 30 - The second cell identifies the particular core clock or gateable 34 - Core clocks 35 - 0 0 APLL [all …]
|