| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
[all …]
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| H A D | omap3xxx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
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| H A D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
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| H A D | omap24xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
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| H A D | omap2420-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2420 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
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| H A D | omap3430es1-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
22 ti,index-starts-at-one;
26 #clock-cells = <0>;
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| H A D | omap2430-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2430 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
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| H A D | omap36xx-omap3430es2plus-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
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| H A D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | ti,composite-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments composite clock
10 - Tero Kristo <kristo@kernel.org>
13 *Deprecated design pattern: one node per clock*
15 This binding assumes a register-mapped composite clock with multiple
16 different sub-types:
18 a multiplexer clock with multiple input clock signals or parents, one
[all …]
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| H A D | composite.txt | 1 Binding for TI composite clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped composite clock with multiple different sub-types;
6 a multiplexer clock with multiple input clock signals or parents, one
9 an adjustable clock rate divider, this behaves exactly as [3]
12 clock, this behaves exactly as [4]
15 merged to this clock. The component clocks shall be of one of the
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
[all …]
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| H A D | divider.txt | 1 Binding for TI divider clock
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped adjustable clock rate divider that does not gate and has
5 only one input clock or parent. By default the value programmed into
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
42 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and max dividers. Optionally
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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| H A D | ti,divider-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments divider clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
14 that does not gate and has only one input clock or parent. By default the
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
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| H A D | ti,mux-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments mux clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
14 signals or parents, one of which can be selected as output. This clock does
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
[all …]
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| H A D | mux.txt | 1 Binding for TI mux clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped multiplexer with multiple input clock signals or
5 parents, one of which can be selected as output. This clock does not
6 gate or adjust the parent rate via a divider or multiplier.
15 register value selected parent clock
20 Some clock controller IPs do not allow a value of zero to be programmed
22 "index-starts-at-one" modified the scheme as follows:
24 register value selected clock parent
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /freebsd/sys/dev/clk/rockchip/ |
| H A D | rk_cru.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 /* Fixed rate clock. */
73 /* Fixed factor multipier/divider. */
88 /* Linked clock. */
101 /* Complex clock fo ARM cores. */
123 /* Fractional rate multipier/divider. */
138 /* Full composite clock. */
142 .clk.composite = &(struct rk_clk_composite_def) { \
157 /* Composite clock without mux (divider only). */
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| /freebsd/sys/arm64/freescale/imx/ |
| H A D | imx_ccm.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
70 struct imx_clk_composite_def *composite; member
77 /* Linked clock. */
90 /* Complex clock without divider (multiplexer only). */
107 /* Fixed frequency clock */
119 /* Fixed factor multipier/divider. */
134 /* Clock gate */
150 /* Root clock gate */
166 /* Composite clock with GATE, MUX, PRE_DIV, and POST_DIV */
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | fsl,sai-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale SAI bitclock-as-a-clock
10 - Michael Walle <michael@walle.cc>
13 It is possible to use the BCLK pin of a SAI module as a generic clock
18 clock of the second SAI as a MCLK clock for an audio codec, for example.
20 This is a composite of a gated clock and a divider clock.
24 const: fsl,vf610-sai-clock
[all …]
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| /freebsd/sys/arm/ti/clk/ |
| H A D | ti_divider_clock.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 * Documentation/devicetree/bindings/clock/ti/divider.txt
74 { "ti,divider-clock", TI_DIVIDER_CLOCK },
75 { "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK },
83 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk()
84 if (sc->clkdom == NULL) { in register_clk()
85 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk()
89 err = clknode_div_register(sc->clkdom, &sc->div_def); in register_clk()
91 DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err); in register_clk()
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6dl-prtvt7.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "imx6qdl-prti6q.dtsi"
9 #include <dt-bindings/display/sdtv-standards.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
23 backlight_lcd: backlight-lcd {
24 compatible = "pwm-backlight";
26 brightness-levels = <0 20 81 248 1000>;
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| /freebsd/contrib/ntp/libntp/ |
| H A D | ntp_calendar.c | 2 * ntp_calendar.c - calendar and helper functions
7 * ---------
[all...] |
| /freebsd/share/dict/ |
| H A D | web2a | 12 A-b-c book
13 A-b-c method
14 abdomino-uterotomy
15 Abdul-baha
16 a-be
20 able-bodied
21 able-bodiedness
22 able-minded
23 able-mindedness
27 Abor-miri
[all …]
|
| H A D | web2 | 37717 clock
40467 composite
56304 divider
99810 Jean-Christophe
99811 Jean-Pierre
|
| /freebsd/contrib/sqlite3/ |
| H A D | sqlite3.c | 17 ** language. The code for the "sqlite3" command-line shell is also in a
20 ** The content in this amalgamation comes from Fossil check-in
54 ** NO_TEST - The branches on this line are not
59 ** OPTIMIZATION-IF-TRUE - This branch is allowed to always be false
63 ** OPTIMIZATION-IF-FALSE - This branch is allowed to always be true
67 ** PREVENTS-HARMLESS-OVERREAD - This branch prevents a buffer overread
72 ** slash-asterisk...asterisk-slash comment marks, with no spaces between the
147 ** 2015-03-02
185 ** large file support, or if the OS is windows, these should be no-ops.
191 ** Large file support can be disabled using the -DSQLITE_DISABLE_LFS switch
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