| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | samsung,exynos-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-d
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| H A D | exynos-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
29 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
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| H A D | synopsys-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ul
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| H A D | rockchip-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <heiko@sntech.de>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
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| H A D | hi3798cv200-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
13 - compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
14 - clocks: A list of phandle + clock-specifier pairs for the clocks listed
15 in clock-names.
16 - clock-names: Should contain the following:
17 "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
18 "biu" - The biu clock described in synopsys-dw-mshc.txt.
19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
20 "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
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| H A D | hisilicon,hi3798cv200-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | altr_socfpga.txt | 1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
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| /freebsd/sys/contrib/device-tree/Bindings/iio/frequency/ |
| H A D | adf4350.txt | 4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
10 ADF435x Reference Clock (CLKIN).
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
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| H A D | adi,adf4350.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
26 description: Clock to provide CLKIN reference clock signal.
28 clock-names:
31 '#clock-cells':
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | realtek,otto-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sander Vanheule <sander@svanheule.net>
14 prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
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| H A D | starfive,jh7100-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
25 - enum:
26 - starfive,jh7100-wdt
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| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | ad5755.txt | 1 * Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
4 - compatible: Has to contain one of the following:
6 adi,ad5755-1
11 - reg: spi chip select number for the device
12 - spi-cpha or spi-cpol: is the only modes that is supported
15 - spi-max-frequency: Definition as per
16 Documentation/devicetree/bindings/spi/spi-bus.txt
19 See include/dt-bindings/iio/ad5755.h
20 - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
23 - adi,dc-dc-phase:
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| H A D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
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| /freebsd/contrib/ntp/kernel/sys/ |
| H A D | timex.h | 21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
28 * Revised status codes and structures for external clock and PPS
45 * ntp_gettime - NTP user application interface
56 * ntp_adjtime - NTP daemon application interface
76 * phase-lock loop (PLL) model used in the kernel implementation. These
97 #define SHIFT_KG 6 /* phase factor (shift) */
105 * possible without overflow of a 32-bit word.
108 * which serves as a an extension to the low-order bits of the system
109 * clock variable time.tv_usec.
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| /freebsd/contrib/ntp/libparse/ |
| H A D | README | 1 PARSE reference clock driver:
22 parsestreams.loadable_module.o - standard parse module for SunOS 4
27 parse - auto loadable streams module
32 The structure of the parse reference clock driver is as follows:
34 ntpd - contains NTP implementation and calls a reference clock
37 - which contains several refclock decriptions. These are
41 (/dev/refclock-0 - /dev/refclock-3).
43 The kind of clock is selected by the mode parameter. This parameter
44 selects the clock type which deterimines how I/O is done,
47 refclock_parse operates on an abstract reference clock
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| /freebsd/contrib/ntp/html/ |
| H A D | discipline.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock Discipline Algorithm</title>
7 <!-- Changed by: stenn, 03-Jan-2020 -->
11 <h3>Clock Discipline Algorithm</h3>
13 <!-- #BeginDate format:En2m -->3-Jan-2020 02:12<!-- #EndDate -->
18 <li class="inline"><a href="#pll">Phase-Lock Loop Operations</a></li>
20 <li class="inline"><a href="#house">Clock Initialization and Management</a></li>
24 …clock discipline algorithm, which is best described as an adaptive parameter, hybrid phase/frequen…
26 <p>Figure 1. Clock Discipline Algorithm</p>
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| H A D | clock.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock State Machine</title>
10 <h3>Clock State Machine</h3>
12 <!-- #BeginDate format:En2m -->4-Aug-2011 23:40<!-- #EndDate -->
25 …and reference implementation a state machine is used to manage the system clock under exceptional …
26 …d upon receipt of an update by the clock discipline algorithm. its primary purpose is to determine…
28 …-of-year (TOY) chip to maintain the time when the power is off. When the computer is restarted, t…
30 …clock discipline gradually slews the clock to the correct time, so that the time is effectively co…
31 …ed and the clock is always slewed. The daemon sets the step threshold to 600 s using the <tt>-x</t…
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| /freebsd/sys/kern/ |
| H A D | kern_ntptime.c | 1 /*-
4 * Copyright (c) David L. Mills 1993-2001 *
22 * Poul-Henning Kamp <phk@FreeBSD.org>.
57 * Single-precision macros for 64-bit machines
61 #define L_SUB(v, u) ((v) -= (u))
63 #define L_NEG(v) ((v) = -(v))
67 (v) = -(-(v) >> (n)); \
77 ((v) = -((int64_t)(-(a)) << 32)); \
81 #define L_GINT(v) ((v) < 0 ? -(-(v) >> 32) : (v) >> 32)
90 * routine is used by the NTP daemon to adjust the system clock to an
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | amlogic,meson-nand.txt | 7 - compatible : contains one of:
8 - "amlogic,meson-gxl-nfc"
9 - "amlogic,meson-axg-nfc"
10 - clocks :
11 A list of phandle + clock-specifier pairs for the clocks listed
12 in clock-names.
14 - clock-names: Should contain the following:
15 "core" - NFC module gate clock
16 "device" - device clock from eMMC sub clock controller
17 "rx" - rx clock phase
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_irig.c | 2 * refclock_irig - audio IRIG-B/E demodulator/decoder
26 * Audio IRIG-B/E demodulator/decoder
29 * IRIG-B/E signals commonly produced by GPS receivers and other timing
30 * devices. The IRIG signal is an amplitude-modulated carrier with
31 * pulse-width modulated data bits. For IRIG-B, the carrier frequency is
32 * 1000 Hz and bit rate 100 b/s; for IRIG-E, the carrier frequenchy is
37 * kHz and mu-law companding. This is the same standard as used by the
43 * The program processes 8000-H
216 double phase, freq; /* logical clock phase and frequency */ global() member
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| /freebsd/share/man/man4/ |
| H A D | spigen.4 | 36 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
54 device is associated with a single chip-select
56 with that chip-select line asserted.
58 SPI data transfers are inherently bi-directional; there are no separate
75 .Bl -tag -width indent
83 .Bd -literal
91 The buffers for the transfer are a previously-mmap'd region.
100 is non-zero, the data appears in the memory region immediately
104 .Bd -literal
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| /freebsd/sys/contrib/device-tree/src/arm64/xilinx/ |
| H A D | zynqmp-sck-kv-g-revB.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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| /freebsd/contrib/ntp/util/ |
| H A D | kern.c | 2 * This program simulates a first-order, type-II phase-lock loop using
21 * Phase-lock loop definitions
24 #define MAXPHASE 512000 /* max phase error (us) */
26 #define TAU 2 /* time constant (shift 0 - 6) */
45 * Phase-lock loop variables
47 int time_status = TIME_BAD; /* clock synchronization status */
51 long time_precision = 1000000 / HZ; /* clock precision (us) */
54 long time_phase = 0; /* phase offset (scaled us) */
90 timey -= 1000000; in main()
93 timex.tv_usec -= 1000000; in main()
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | renesas,rz-mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu
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