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/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h3 functions, file path functions, and CPU architecture-specific functions.
5 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
6 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
10 Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
12 SPDX-License-Identifier: BSD-2-Clause-Patent
20 // Definitions for architecture-specific types
24 /// The IA-32 architecture context buffer used by SetJump() and LongJump().
56 UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
131 Reads the current value of CNTPCT_EL0 register.
133 Reads and returns the current value of CNTPCT_EL0.
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H A DPcdLib.h9 translated to a variable or macro that is auto-generated by build tool in
17 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
18 SPDX-License-Identifier: BSD-2-Clause-Patent
41 Returns the Boolean value for the PCD feature flag specified by TokenName.
45 @param TokenName The name of the PCD token to retrieve a current value for.
47 @return Boolean value for the PCD feature flag.
53 Retrieves an 8-bit fixed PCD token value based on a token name.
55 Returns the 8-bit value for the token specified by TokenName.
59 @param TokenName The name of the PCD token to retrieve a current value for.
61 @return 8-bit value for the token specified by TokenName.
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H A DBaseMemoryLib.h4 The Base Memory Library provides optimized implementations for common memory-based operations.
8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
23 If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
24 If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT().
42 Fills a target buffer with a byte value, and returns the target buffer.
44 This function fills Length bytes of Buffer with Value, and returns Buffer.
46 If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
50 @param Value The value with which to fill Length bytes of Buffer.
60 IN UINT8 Value
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dia32intrin.h1 /* ===-------- ia32intrin.h ---------------------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
29 /// Finds the first set bit starting from the least significant bit. The result
38 /// A 32-bit integer operand.
39 /// \returns A 32-bit integer containing the bit number.
46 /// Finds the first set bit starting from the most significant bit. The result
55 /// A 32-bit integer operand.
56 /// \returns A 32-bit integer containing the bit number.
60 return 31 - __builtin_clz((unsigned int)__A); in __bsrd()
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H A Demmintrin.h1 /*===---- emmintrin.h - SSE2 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __target__("sse2,no-evex512"), __min_vector_width__(128)))
57 __target__("mmx,sse2,no-evex512"), __min_vector_width__(64)))
59 /// Adds lower double-precision values in both operands and returns the
61 /// are copied from the upper double-precision value of the first operand.
68 /// A 128-bit vector of [2 x double] containing one of the source operands.
70 /// A 128-bit vector of [2 x double] containing one of the source operands.
71 /// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
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H A D__wmmintrin_aes.h1 /*===---- __wmmintrin_aes.h - AES intrinsics -------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
21 /// Inverse Cipher, transforming the state value from the first source
22 /// operand using a 128-bit round key value contained in the second source
30 /// A 128-bit integer vector containing the state value.
32 /// A 128-bit integer vector containing the round key value.
33 /// \returns A 128-bit integer vector containing the encrypted value.
41 /// Inverse Cipher, transforming the state value from the first source
42 /// operand using a 128-bit round key value contained in the second source
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H A Davxintrin.h1 /*===---- avxintrin.h - AVX intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
57 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
61 /// Adds two 256-bit vectors of [4 x double].
68 /// A 256-bit vector of [4 x double] containing one of the source operands.
70 /// A 256-bit vector of [4 x double] containing one of the source operands.
71 /// \returns A 256-bit vector of [4 x double] containing the sums of both
79 /// Adds two 256-bit vectors of [8 x float].
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H A Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \
40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
54 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
64 /// Adds two 128-bit vectors of [4 x float], and returns the results of
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H A Df16cintrin.h1 /*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
29 /// value.
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
47 /// half-precision float value.
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H A Draointintrin.h1 /*===----------------------- raointintrin.h - RAOINT ------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
31 /// A pointer to a 32-bit memory location.
33 /// A 32-bit integer value.
42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
53 /// A pointer to a 32-bit memory location.
55 /// A 32-bit integer value.
64 /// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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H A Dlwpintrin.h1 /*===---- lwpintrin.h - LWP intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
60 /// A 32-bit value is zero-extended and inserted into the 64-bit Data2 field.
62 /// A 32-bit value is inserted into the 32-bit Data1 field.
64 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
73 /// Decrements the LWP programmed value sample event counter. If the result is
82 /// A 32-bit value is zero-extended and inserted into the 64-bit Data2 field.
84 /// A 32-bit value is inserted into the 32-bit Data1 field.
86 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
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H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
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/freebsd/share/man/man3/
H A Dbitstring.382 .Nd bit-string manipulation functions and macros
90 .Fn bit_clear "bitstr_t *name" "size_t bit"
92 .Fn bit_count "bitstr_t *name" "size_t count" "size_t nbits" "ssize_t *value"
94 .Fn bit_ffc "bitstr_t *name" "size_t nbits" "ssize_t *value"
96 .Fn bit_ffs "bitstr_t *name" "size_t nbits" "ssize_t *value"
98 .Fn bit_ffc_at "bitstr_t *name" "size_t start" "size_t nbits" "ssize_t *value"
100 .Fn bit_ffs_at "bitstr_t *name" "size_t start" "size_t nbits" "ssize_t *value"
102 .Fn bit_ff_at "bitstr_t *name" "size_t start" "size_t nbits" "int match" "ssize_t *value"
104 .Fn bit_ffc_area "bitstr_t *name" "size_t nbits" "size_t size" "ssize_t *value"
106 .Fn bit_ffs_area "bitstr_t *name" "size_t nbits" "size_t size" "ssize_t *value"
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DInstructionUtils.h1 //===-- InstructionUtils.h --------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 // Common utilities for manipulating instruction bit fields.
19 // Return the bit field(s) from the most significant bit (msbit) to the
20 // least significant bit (lsbit) of a 64-bit unsigned value.
24 return (bits >> lsbit) & ((1ull << (msbit - lsbit + 1)) - 1); in Bits64()
27 // Return the bit field(s) from the most significant bit (msbit) to the
28 // least significant bit (lsbit) of a 32-bit unsigned value.
32 return (bits >> lsbit) & ((1u << (msbit - lsbit + 1)) - 1); in Bits32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries -------
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/freebsd/sys/contrib/edk2/Include/Protocol/
H A DPiPcd.h6 PI PCD protocol only provide the accessing interfaces for Dynamic-Ex type PCD.
11 information is stored (such as in Read-only data, or an EFI Variable).
12 This protocol allows access to data through size-granular APIs and provides a mechanism for a
15 Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
16 SPDX-License-Identifier: BSD-2-Clause-Patent
35 For each item (token), the database can hold a single value that applies to all SKUs, or multiple
36 values, where each value is associated with a specific SKU Id. Items with multiple, SKU-specific
39 not SKU enabled, the system ignores any set SKU Id and works with the single value for that token.
40 For SKU-enabled tokens, the system will use the SKU Id set by the last call to SetSku(). If no SKU
42 …SKU Id. If the system attempts to use the default SKU Id and no value has been set for that Id, the
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H A DPcd.h5 PCD protocol provide interfaces for dynamic and dynamic-ex type PCD.
7 but interfaces in dynamic-ex type PCD require token space guid as parameter.
9 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
28 Sets the SKU value for subsequent calls to set or get PCD token values.
33 For each item (token), the database can hold a single value that applies to all SKUs,
34 or multiple values, where each value is associated with a specific SKU Id. Items with multiple,
35 SKU-specific values are called SKU enabled.
39 single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the
41 …the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value …
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
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/freebsd/sys/contrib/dev/rtw88/
H A Dfw.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
32 #define RTW_DEFAULT_CQM_THOLD -70
99 #define RTW_C2H_RA_RPT_SGI BIT(7)
145 FW_FEATURE_SIG = BIT(0),
146 FW_FEATURE_LPS_C2H = BIT(1),
147 FW_FEATURE_LCLK = BIT(2),
148 FW_FEATURE_PG = BIT(3),
149 FW_FEATURE_TX_WAKE = BIT(4),
150 FW_FEATURE_BCN_FILTER = BIT(5),
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
37 Value type: string
38 Definition: "ibm,powerpc-cpu-features"
45 - isa
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
23 description: u32 value representing the anatop MFD register offset.
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7)
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/freebsd/share/man/man9/
H A Dieee80211_radiotap.960 layer used by 802.11 drivers includes support for a device-independent
68 Radiotap was designed to balance the desire for a hardware-independent,
93 With radiotap setup, drivers just need to fill in per-packet
105 .Bd -literal -offset indent
115 .Bd -literal -offset indent
129 .Bl -tag -width indent
131 This field contains the unsigned 64-bit value, in microseconds,
133 In theory, for each received frame, this value is recorded
134 when the first bit of the MPDU arrived at the MAC.
138 This field contains a single unsigned 8-bit value, containing one or
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/freebsd/sys/dev/cxgbe/cudbg/
H A Dcudbg_wtp.c1 /*-
258 struct adapter *padap = pdbg_init->adap; in read_sge_debug_data()
259 u32 value; in read_sge_debug_data() local
264 value = t4_read_reg(padap, A_SGE_DEBUG_DATA_LOW); in read_sge_debug_data()
265 /*printf("LOW 0x%08x\n", value);*/ in read_sge_debug_data()
266 sge_dbg_reg[(i << 1) | 1] = HTONL_NIBBLE(value); in read_sge_debug_data()
267 value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH); in read_sge_debug_data()
268 /*printf("HIGH 0x%08x\n", value);*/ in read_sge_debug_data()
269 sge_dbg_reg[(i << 1)] = HTONL_NIBBLE(value); in read_sge_debug_data()
277 struct adapter *padap = pdbg_init->adap; in read_tp_mib_data()
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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h1 //===-- llvm/ADT/APInt.h - For Arbitrary Precision Integer -----*- C++ -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
41 inline APInt operator-(APInt);
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
50 /// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-width
51 /// integer sizes and large integer value types such as 3-bits, 15-bits, or more
52 /// than 64-bits of precision. APInt provides a variety of arithmetic operators
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